AVR单片机的秒表程序，最大计时可达9分59秒9。

8051工作于11.0592MHZ,RAM扩展为128KB的628128,FlashRom扩展为128KB的AT29C010A 128KB的RAM分成4个区(Bank) 地址分配为0x0000-0x7FFF 128KB的FlashRom分成8个区(Bank) 地址分配为0x8000-0xBFFF 为了使8051能访问整个128KB的RAM空间和128KB的FlashRom空间,在CPLD内建两个寄存器 RamBankReg和FlashRomBankReg用于存放高位地址-8051 works in 11.0592MHZ, RAM expansion for the 128KB of 628128, FlashRom extended AT29C010A 128KB to 128KB of the RAM is divided into four zones (Bank) Address Assignment for the 0x0000-0x7FFF 128KB FlashROM divided into eight zones (Bank) Address Assignment for the 0x8000- 0xBFFF in order to enable the 8051 to access the entire 128KB and 128KB of RAM space of FlashROM space, two built-in CPLD register RamBankReg and used to store high FlashRomBankReg Address

应用背景The CMX990 provides, on-chip: a flexible, formattable GMSK packet and freeformat modem, a dual synthesiser fed from an external source, IF and RF transceiver stages for both Rx and Tx modes, and auxiliary ADCs and DACs for system control and monitoring.关键技术Operating in the range of 400MHz to 1GHz at data rates of 4 to 16 kbps. This single-chip, half-duplex device requires a minimum of external components, keeping end-product board size, power consumption and cost to an absolute minimum. The versatile GMSK modem is configured for either packet and freeformat data operation via an efficient task-oriented Rx and Tx format and command structure combined with data scrambling, interleaving and FEC and CRC capabilities. Rx data acquisition, extraction and tracking functions use Rx data-quality feedback to support varying signal environments. IF and RF functions in the Tx path handle all the signal processing requi

本例演示如何配置提姆周在PWM（脉冲宽度调制方式）。四PWM信号产生不同的占空比送入机器人CC电机相。显示菜单以不同转速之间选择

basicusb(演示USB设备基本操作的程序源代码)-basicusb (demo USB devices basic operation of the program source code)

伟福仿真器软件使用- Great lucky simulator software uses

几个嵌入式MYSQL编程示例，包含了MYSQL带的动态库-Several programming examples embedded MYSQL, MYSQL belt contains the dynamic libraries

应用背景Abstract—Leros is a tiny microcontroller that is optimized for current low-cost FPGAs. Leros is designed with a balanced logic to on-chip memory relation. The design goal is a microcontroller that can be clocked in about half of the speed a pipelined on-chip memory and consuming less than 300 logic cells. The architecture, which follows from the design goals, is a pipelined 16-bit accumulator processor. An implementation of Leros needs at least one on-chip memory block and a few hundred logic cells. The application areas of Leros are twofold: First, it can be used as an intelligent peripheral device for auxiliary functions in an FPGA based system-on-chip design. Second, the very small size of Leros makes it an attractive softcore for many-core research with low-cost FPGAs.关键技术The smallest core is comparable to Leros and can be implemented

ucos在嵌入式平台上移植的一般方法和技巧-ucos transplantation in the embedded platform, the general methods and techniques

ARM7的ads环境下的画圆的实现，在用户环境下得应用！采用周立功公司的LPC2103系列的板子！-ARM7-under ads drawcircle the implementation, a user application environment! Ligong weeks using the company" s board LPC2103 series!

工作由 implementear 任务 （周期性和非周期性） 组成和其使用 Xenomai 事件处理程序