C6000 Series DSP hardware design and development. Video

Java in a nut shell,非常不错的书-Java in a nut shell,very good.

大名鼎鼎的TEEChart，大家一定听说过吧，VC源代码 大家下载下来卡看-The famous TEEChart, everyone must have heard of bar, VC source code you downloaded card to see

jdbc书，很适合初学者学习数据库编程-jdbc book, which is perfect for beginners to learn database programming

c++完美演绎的源代码-c perfect interpretation of the source code

《魔兽世界官方小说》作者：理查德 A[1].克纳卡,电子书版，阅读方便！ U9联盟 a116054717制作-World of Warcraft Official novel Author: Richard A [1]. Kena Ka, e-book version, read the easy!

C语言编程宝典之一-C programming language one of the book

关于FPGA流水线设计的论文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.-FPGA pipelined designs on paper This work invest

IPSEC的中文文档，详细描述了IPSEC的机制，并实现了IPSEC。

VC++ 编程指南.chm-VC Programming Guide. Chm

学生成绩管理系统，java语言，数据库课程设计-Student performance management system, java language, database curriculum design