VHDL 2008 A reference book on VHDL

基于网口的收发数据及解析数据内容的verilog代码实现(Based on the Internet port to send and receive data and parse the contents of the data verilog code)

说明：  uart implementation and documentation, this describes the basic steps in building your own uart module on verilog and programming them on an fpga device

FPGA中按键弹跳消除模块的研究与应用，原理和例子都非常好-FPGA to eliminate bounce in key research and application modules, principles and examples are very good

同步串行数据发送电路SSDT的基本功能是将并行数据转换成串行数据并进行同步发送。系统写入和读出时序完全兼容Intel8086时序。 系统以同步信号开始连续发送四个字节，在发送中出现5个1时插入一个0，在四个数据发送结束而下一次同步没有开始之前，发送7FH，这时中间不需要插入零 -synchronous serial data transmission circuit SSDT the basic function is to convert parallel data into serial and the same this step. System write and read sequential fully compatible Intel8086 timing. Synchronized signal system to start sending four consecutive bytes, in this emerging 5 1:00 insert a 0, at the end of four data sent and the next synchronization not started before, sending seven FH, then the middle is not inserted

VHDL的基本数学运算库,非常好用-VHDL basic arithmetic library, a very handy! !

加密已经成为我们生活的一部分，我们

基于fpga的led点阵控制系统软件程序设计(Led dot matrix control system based on fpga software program design)

实验用16位全加器的VHDL代码，适合初学者学习，数电学习的好工具。 (Experiment with 16-bit full adder VHDL code for beginners to learn, a good tool to learn a few power.)

说明：  how to come ture a costas loop in FPGA with verilog,it is very useful on project

VHDL的基本程序，可以用来驱动键盘，功能强大，虽然和基础-VHDL