1K SRAM独立的读写端口，Verilog代码的ASIC设计

说明：  单周期cpu，使用verilog编写的的单周期cpu支持......等功能(Single cycle CPU, using Verilog written single cycle CPU support... And other functions)

A design on a DE270 FPGA with the use of CCD: a camera DC2 and a TRDB LTM after reading from the SRAM.

rs422标准通讯模块 异步收发 verilog语言编写(rs422 standard communication module asynchronous receiver verilog language)

暑期实习，基于FPGA的电子琴，任意分频。                                                                                                                                                                

16QAM,64QAM,256QAM调制下的球形译码(16QAM, 64QAM, 256QAM modulation sphere decoding)

RS（255，223）编码器，已实际运用到产品中(RS (255,223) encoder has actually applied to products)

Xilinx开发板ML505的DDRII示例程序，使用Verilog，调用MIG，编译环境ISE11.1(Xilinx ML505 development board of DDRII sample program, using Verilog, called MIG, build environment ISE11.1)

this files describes how to build i2c block modules in verilog hdl and programming them on an fpga device

三维离散小波变换的代码

VHDL之二進制轉BCD碼之程式碼，算完整的(Of binary to BCD code VHDL code, operator complete)