-
arduino 液晶屏
dogm128 库更新日志
2010-02-13 v1.00 奥利弗 Kraus < olikraus@gmail.com >
* 第一版
2010-07-17 v1.01 奥利弗 Kraus < olikraus@gmail.com >
* 固定编译器警告
* 修正了一个在 Breakorino
* 实施 getStrWidth 函数 (十三期)
* 添加了新示例"Stars.pde"
* 添加位图支持 (例如"Walk.pde")
* 少闪存 ROM 所需 (函数放入单独的文件)
* 在 drawArc 修正 bug (w0 > w1)
* 添加 GraphicsTest.pde
2010-07-18 v1.02 奥利弗 Kraus < olikraus@gmail.com >
* 删除不是必需的文件
2010-08-19 v1.03 奥利弗 Kraus < olikraus@gmail.com >
* 代码更新: DOG_WIDTH 如果需要使用
* 支持 DOGM132 和 DOGS102
* 新级别 4 和 5 的 Breakorino
* 添加 SPI 抽象层 (dogmspi.c)
* 更通用的延迟过程 (dog_delay())
* clrHLine xorHLine
2010-09-05 v1.04 奥利弗 Kraus < olikraus@gmail.com >
* 重命名 dog_delay()--> dog_Delay()
* 重命名 dog_init()--> dog_Init()
* 重命名 dog_set_inverse()--> dog_SetInvertPixelMode()
* 重命名 dog_set_contrast()--> dog_SetCont
- 2022-03-07 18:53:32下载
- 积分:1
-
使用凌阳61单片机和1302时间芯片完成时钟功能并使用CH451LS芯片显示(程序中只在0号LED上显示秒)。是使用时,main.c是1302时间芯片的驱动,C...
使用凌阳61单片机和1302时间芯片完成时钟功能并使用CH451LS芯片显示(程序中只在0号LED上显示秒)。是使用时,main.c是1302时间芯片的驱动,CH451LS0811.h是简单CH451LS芯片驱动。-The use of Sunplus 61-chip MCU and 1302 hours to complete and use the clock function CH451LS chip display (program only in its LED display 0 seconds). Is used, main.c is the 1302 driver chip time, CH451LS0811.h is simple chip CH451LS drive.
- 2022-01-30 18:32:28下载
- 积分:1
-
pcmic初始代码!
pcmic初始代码!--Startup code for pcmic.
- 2023-08-20 19:30:03下载
- 积分:1
-
running character on lcd on LM016L
这段代码将显示一个单独的字符,将单独运行,它将提取一个字符。从存储字符串
- 2022-03-19 22:24:32下载
- 积分:1
-
进程管理的模拟
进程管理的模拟-Process management simulation
- 2022-04-29 17:50:15下载
- 积分:1
-
基于C51实现C语言编程LCD动态显示0~7 8位
基于C51实现C语言编程LCD动态显示0~7 8位-lcd lcd lcd lcd lcd lcd lcd lcd lcd
- 2022-05-19 21:02:43下载
- 积分:1
-
mike hi
mike hi-tech c tools
- 2022-01-27 09:05:45下载
- 积分:1
-
fpga实用倍频电路
fpga实用倍频电路-Frequency Circuit
- 2022-08-20 13:32:33下载
- 积分:1
-
用C进行嵌入式开发的一个完整的面向中级用户的讨论
用C进行嵌入式开发的一个完整的面向中级用户的讨论-C embedded with the development of a complete discussion of user-oriented intermediate
- 2022-01-30 17:46:03下载
- 积分:1
-
A Tiny Microcontroller for FPGAs
应用背景Abstract—Leros is a tiny microcontroller that is optimized for
current low-cost FPGAs. Leros is designed with a balanced logic
to on-chip memory relation. The design goal is a microcontroller
that can be clocked in about half of the speed a pipelined on-chip
memory and consuming less than 300 logic cells.
The architecture, which follows from the design goals, is a
pipelined 16-bit accumulator processor. An implementation of
Leros needs at least one on-chip memory block and a few hundred
logic cells.
The application areas of Leros are twofold: First, it can be used
as an intelligent peripheral device for auxiliary functions in an
FPGA based system-on-chip design. Second, the very small size
of Leros makes it an attractive softcore for many-core research
with low-cost FPGAs.关键技术The smallest core is comparable to Leros and can be implemented
- 2023-09-03 01:00:04下载
- 积分:1