C8051F020 prepared with RA8803 LCD controller 320,240 procedures

PIC16F877应用的AD转换主程序 并可以通过LCD显示-PIC16F877 applications AD conversion by the main program and LCD display

基于NXP51单片机LPC932电子时钟的设计（致远公司学生用开发板）-LPC932 Singlechip NXP51 based on the design of the electronic clock (TOWIN company for student development board)

这是新华龙（www.xhl.xom.xn）开发的，基于单片机，现在可以在它的网站上免费下载，不过当初他可是花了500大元买的。 --It is developed by www.xhl.xom.xn and based on SCM.

此程序是用于AVR单片机驱动FLASH的,对于用AVR单片机进行开发的朋友,提供了一个例程,还有对于对使用FLASH没有经验的朋友也有很好参考价值-this procedure is used AVR Flash Drive, AVR for use for the development of a friend, provides a routine, There FLASH for the right to use the lack of experience has become a good friend reference value

摘要：提出了一种基于单片机与AD9852的信号源的实现，重点介绍了单片机与AD9852硬件接口电路、AD9852串行工作流程以及宽带滤波器设计的关键技术。 关键词：AD9852；信号发生器；频率合成

监控矩阵系统视频字符叠加,128路视频输入/32路视频输出.-Surveillance video characters superimposed matrix system, 128 video input/video output 32.

电子秒表的设计 1、用系统8253定时器提供的55ms定时单位，设计秒表定时程序。 2、有关系统定时方法： PC机系统中的8253定时器0工作于方式3，外部提供一个时钟作为CLK信号, 频率：f=1.1931816MHz。 定时器0输出方波的频率:fout=1.1931816/65536=18.2Hz。 输出方波的周期Tout=1/18.2=54.945ms。8253A每隔55ms引起一次中断-Electronic stopwatch design one, using the system timer 8253 provides 55ms timing units, design stopwatch timing procedures. 2, the system timing method: PC system timer 0 of 8253 working in the way of 3, to provide an external clock as the CLK signal, the frequency: f = 1.1931816MHz. Timer 0 output square wave frequency: fout = 1.1931816/65536 = 18.2Hz. Cycle square wave output Tout = 1/18.2 = 54.945ms. 8253A every 55ms caused a disruption

8位定时器H1(PWM 输出) -8-bit timer H1 (PWM output)

《单片机原理与实用技术》第10章-"SCM principles and practical technology," Chapter 10

本系统参照片上系统的设计架构、采用FPGA与SPCE061A相结合的方法，以SPCE061A单片机为进程控制和任务调度核心；FPGA做为外围扩展，内部自建系统总线，地址译码采用全译码方式。FPGA内部建有DDS控制器，单片机通过系统总线向规定的存储单元中送入正弦表；然后DDS控制器以设定的频率，自动循环扫描，生成高精度，高稳定的5Hz基准测量信号。-The system with reference to the design of system-on-chip architecture, used a combination of FPGA and SPCE061A approach to SPCE061A Singlechip for process control and scheduling core mission FPGA for external expansion, internal self-system bus, address decoding using the entire translated code approach. DDS has built internal FPGA controller, microcontroller through the system bus to the provisions of the storage unit into the sine table DDS controller and then to set the frequency, automatic cycle of scanning, to generate high precision and high stability of the baseline measurement 5Hz signal.