Simulation Study on Grid Integration and Steady Operation of Doubly

网站的功能需求分析，可以作为刚入行的新人进行参阅，写的还不错-Site analysis of functional requirements, can be used as new recruits to see, written in good

1.模拟并发进程共享的临界资源m1、m2，它联系着两个信号量sem1、sem2. 2.模拟并发进程的运行现场：通用寄存器i,程序计数器addr. 3.模拟三个并发进程.-1. Simulation of the process of sharing with the critical resources m1 and m2, it is tied to the volume of two signals sem1, sem2. 2. Simulation of the process of running with the scene : Definitive register i, procedures counter addr. 3. Three concurrent simulation process.

1．任意选取一个灰度图像和彩色图像，对算法中若干关键语句中的参数进行调整，得出不同的实验结果，并对这些结果进行分析。 2．根据自己所学知识，提出自己的轮廓线提取方法，与简单阈值法进行比较分析。 3．练习matlab自带算子的检测结果。 -1. Arbitrarily select a gray-scale images and color images, several key statements on the algorithm to adjust the parameters, results in different experimental results, and these results were analyzed. 2. Learned based on their knowledge, put forward its own contour extraction method, with a simple threshold method for comparative analysis. 3. Matlab built-operator practice test results.

包含1994年至2007年电子设计大赛历届题目-Contain from 1994 to 2007 Electronic Design Contest Previous topic

基于STM32三相多功能电能表解决方案（典型的实用方案）-three phase meter based stm32 chip

... 公司授权正版用户可以使用这些程序的源代码，但必须标明由易语言编写及易语言网址。 其中：连连看、易之表增强版与中华 ... 农历月历支持库 拖放支持库 正则表达式支持库 进程通讯支持库 BT下载支持库 网络通讯支持库二 超级选择夹支持库-... Genuine authorized users can use a program"s source code, but easy to be labeled by the Yi language and language website. Of which : 1000 block of Terry Avenue and replace it with an enhanced version table ... the Chinese Lunar Calendar supports the drag-and-drop support for regular expressions support for the process of communication support for BT download support for network communications support for two Super folder support for choice

基于FPGA的增量式光电编码器计数电路设计,文章含有Verileg HDL代码.-FPGA-based incremental photoelectric encoder count circuit design, the article contains Verileg HDL code.

本文介绍一种以CPLD[1]为核心、以VHDL[2]为开发工具的时间控制器，该控制器不仅具有时间功能，而且具有定时器功能，能在00：00～23：59之间任意设定开启时间和关闭时间，其设置方便、灵活，广泛应用于路灯、广告灯箱、霓虹灯等处的定时控制。-This article describes a CPLD [1] as the core, VHDL [2] for the development of tools for time controller that features not only has the time, but with the timer function, can be between 00:00 ~ 23:59 arbitrarily set to open time and closing time, and its convenient, flexible, widely used in street lamps, advertising light boxes, neon lights, etc. The timing control.

mathlab for image processing 2D, DFT, FFT etc.

本书为杨小牛的《软件无线电原理和应用》，供学习软件无线电的同学参考-Yang Mavericks book for the