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Composition Principle of Computer Animation, clear introduction to the compositi...
计算机组成原理动画演示,清晰的介绍了组成原理中的重要原理的动画演示,直观明了-Composition Principle of Computer Animation, clear introduction to the composition of the important tenets of the principle of animated demo, intuitive understanding of
- 2022-08-10 04:51:30下载
- 积分:1
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VC+++课程设计程序加论文++源代码有注释
VC+++课程设计程序加论文++源代码有注释-VC+++ processes in curriculum design papers++ source code annotated
- 2022-05-23 07:19:27下载
- 积分:1
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这是一个用VHDL语言写的数码管程序.有用着
这是一个用VHDL语言写的数码管程序.有用着-This is a VHDL language used to write the digital tube procedures. Useful to an
- 2022-05-08 05:37:10下载
- 积分:1
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在足球比赛中,操作系统在语言的发展过程中,是足球成绩…
在symbian os 上运行,开发语言是symbian c++,和标准c++有点区别。演示了标准的在symbian 显示文本的方式。入门级程序代码-in football scores os running on the development of language is football scores c, c and standards somewhat different. Demonstration of the standard text in football scores show the way. Entry-level code
- 2022-06-26 18:47:16下载
- 积分:1
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一种PPT格式。
a type of ppt format.
- 2022-07-14 04:56:25下载
- 积分:1
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EWB做的多功能数字钟
由振荡器输出稳定的高频脉冲信号作为时间基准,经分频器输出标准的秒脉冲,秒计数器满60向分计数器进位,分计数器满60向小时计数器进位...
EWB做的多功能数字钟
由振荡器输出稳定的高频脉冲信号作为时间基准,经分频器输出标准的秒脉冲,秒计数器满60向分计数器进位,分计数器满60向小时计数器进位,小时计数器按“12翻1”规律计数,计数器经译码器送到显示器;计数出现误差可用校时电路进行校时、校分、校秒,
可发挥部分:使闹钟具有可整点报时与定时闹钟的功能。
-EWB done by the multi-function digital clock oscillator output stable high frequency pulse signal as a time reference. Frequency Divider output by the standards of seconds pulse, aged 60 seconds to counter-counter rounding, Counter-to-60-hour counter rounding, by the Counter-hour "12 over a" law count, Counter by the decoder to display; Counting errors school circuit can be used for schools, school hours, school seconds to play : The alarm clock can be made with whole point regular alarm clock and timer functions.
- 2023-04-15 03:10:03下载
- 积分:1
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realize the systray for your running program
realize the systray for your running program
- 2022-05-27 10:01:48下载
- 积分:1
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黄金版w32dsm8.93需要快速下载
W32dsm8.93 黄金版,需要的赶紧下载-Gold Edition W32dsm8.93 needs quickly download
- 2023-08-25 14:20:05下载
- 积分:1
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时钟由Verilog可计数从00:00至23:59写作。带一个文件到…
A clock writing by Verilog which can count from 00:00 to 23:59. With a C file to see the simulation results. A co-design example of C and Verilog.
- 2022-10-19 21:25:03下载
- 积分:1
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三维刚体极限平衡法计算包,功能包括施加锚索力、地震力,并可以考虑地下水作用...
三维刚体极限平衡法计算包,功能包括施加锚索力、地震力,并可以考虑地下水作用-Three-dimensional rigid body limit equilibrium method to calculate package, features include the ability to impose anchor, earthquake forces, and can consider the role of groundwater
- 2022-08-23 05:23:14下载
- 积分:1