FPGA 乒乓球

verilog语言实现一个CPU，汇编程序实现汉明编码功能，输入11位代码，输出15位编码结果。(Verilog language to achieve a CPU, assembler to achieve Hamming coding function, enter 11 bit code, output 15 bit encoding results.)

verilog语言设计的VGA驱动。在Quarus11.0下编译成功，并在Altera cyclone4开发板上测试OK(verilog language design VGA driver. In Quartus11.0 successfully compiled and Altera cyclone4 development board test OK)

本程序可以在DE1-SOC的实现10进制的FPGA数字计数器

Time divisor vhdl code

BUS documentation and map reffereces

说明：  我测试过的！Verilog HDL实现RS编码。(I' ve tested it! RS coding Verilog HDL implementation.)

使用verilog语言编写的colorbar输入，适合于用于图像采集系统的测试和验证用。

本代码为h.264解码器的Verilog代码，在本压缩包中包含了全部Verilog代码，亲测成功，可以使用。

数字滤波器组。包含matlab程序和word说明。通过一个低通数字滤波器和多个带通数字滤波器组合成一个滤波器组(Groups of the digital filter. Contains matlab program and word description. Through the combination of a low pass digital filter, and a plurality of band-pass digital filter into a filter bank)

VGA controller : Genarate a VGA signal from your inout information as color info of each pixel