基于TinyOS系统在CC2530下的点灯程序

gobee j2me

Modicon Modbus Serial Driver for Intellution iFIX version 7

自己写的Viterbi Decoder 可以解码 213 417 码率-Viterbi decoder for 213 417 code rate

J2ME编写的手机游戏（诺基亚）-J2ME prepared by the mobile gaming (Nokia)

现有数字信号自动调制识别方法大多只适用于无记忆信号，如PSK、ASK、FSK信号等。将有记忆 信号(MSK信号)和无记忆信号一起考虑，提出了一种改进的数字信号自动识别方法。该方法采用信号的瞬时统 计量作为特征参数，采用多层神经网络作为分类器。计算机仿真表明：当噪声采用高斯白噪声，并且信噪比大于 l5 dB时，识别率高于96％ ；当信噪比不低于l0 dB时，识别率不低于90％。-Existing digital signal automatic modulation recognition methods are mostly applied only to memoryless signals, such as PSK, ASK, FSK signals. Will have a memory signal (MSK signal) and non-memory signal into consideration, an improved digital signal automatic identification method. This method is the use of the instantaneous signal statistics as a characteristic parameter, the use of multi-layer neural network as classifier. Computer simulation shows that: When the noise using Gaussian white noise, and signal to noise ratio greater than l5 dB, the recognition rate is higher than 96 when the signal to noise ratio not less than l0 dB, the recognition rate of not less than 90.

雷达直达波和目标回波之间抵消，两个信号一强一弱，既可以抵消强信号，也可以抵消弱信号-Radar direct wave and the target echo offset between the two signals a strong one weak, only to be offset by a strong signal, you can also offset the weak signal

应用背景this main described the Auburn University Electrical and Computer Engineering and the theroy of the “Moore’s Law” for Wireless,described the Qualcomm’s 1000x Mobile Data Challenge.关键技术Small (residential) cellular base stations (FBS) ,Deployed by clients,Internet connection to the Macro Base Station (MBS),Operate at a power of 20mW and up to 10 meters,Provide better indoor coverage Offload data from the macrocell. Bachelor of Wireless Engineering (BWE): ABET-accredited program and The first-of-its-kind in the nation.

资源描述STM8lFreeModbus源代码程序 非常详细的内容 并且我移植的很成功，目前已经用在项目上

从《无线通信FPGA设计》一书中摘录下来的WCDMA系统小区搜索的FPGA实现第三部分代码。-From the " Wireless FPGA Design" a book excerpt down the WCDMA system cell search FPGA to achieve the third part of the code.

verilog编写的时钟控制程序，在xilinx芯片上开发。具有案件防抖等考虑，-Verilog clock control procedures to prepare, in the Xilinx chip development. Anti-shake, such as with the case considered