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最大似然（ML）准则和最大后验概率（MAP）准则Matlab仿真-Maximum Likelihood (ML) criteria and maximum a posteriori probability (MAP) criteria Matlab simulation

时钟发生器，可以显示分，秒，小时，下到ＦＰＧＡ上验证过，功能基本正常-clock generator can demonstrate minutes and seconds, hours, the next to the FPGA tested normal function

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不错的beijingfenge的程序，c语言写的，适合对fenge感兴趣的的初学者和编程人员。-Good beijingfenge procedures, c language, and suitable for fenge interest of beginners and programmers.

资源描述代码包括dra808m模块配置。模块是由多吉和它是一个良好的收发模块，包括代码的配置发送和接收的频率和音量等编程是Arduino平台做

]本文介绍了如何利用CPLD(复杂可编程逻辑器件)与单片机的结合实现并行I／ O(输入／输出)接口的扩展。该设计与用8255做并行I／O接口相比，与单片机软件完全兼容， 同时拥有速度快，功耗低，价格便宜，使用灵活等特点-] This article describes how to use the CPLD (complex programmable logic device) and the single-chip combination to achieve parallel I/O (input/output) interface expansion. The design and use 8255 to do parallel I/O interface as compared with the single-chip software is fully compatible at the same time have a fast, low power consumption and cheaper prices, the use of flexible features such as

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DSPTI C6000 ZBTRAM的使用历程，初学者必读-DSPTI C6000 ZBTRAM the use of the course, the required reading beginners