关于boost graph library的文档，值得好好研究一下

win2kDDK中文翻译版描述如何里基本的DDK内容-win2kDDK describes how the Chinese translation version of the DDK in the basic content

Tai lieu CCNA tieng viet

Pricinples and fundamentals of electrical engineering-Pricinples and fundamentals of electrica l engineering

System will automatically delete the directory of debug and release, so please do not put files on these two directory.

数据窗口是PB的一大特色. 本文尽可能详细的介绍了PowerBuilder 7数据窗口技术-PB data window is the one major feature. In this paper, as detailed introduction to the PowerBuilder window seven technical data

本电子书籍为java-electronic books for java

mfc资源大全包含MFC编程各个方面的源码-mfc resources Daquan MFC programming includes all aspects of FOSS

是关于WINSOCK的一些内容介绍,实用价值并不是很高,但是在快速复习WINSOCK时,还是能帮上不少忙

关于FPGA流水线设计的论文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.-FPGA pipelined designs on paper This work invest

Eamon O’Tuathail的WTL开发者指南英文版-WTL Developer Guide