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uart01
一种实现计算机接口rs232与FPGA通信的基于VHDL语言设计的一段非常简洁的程序(A RS232 computer interface implementation with FPGA-based VHDL language communications designed a very simple procedure)
- 2009-03-15 23:13:42下载
- 积分:1
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gtx
ip core of the transceiver gtx
- 2019-04-02 00:10:03下载
- 积分:1
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Shumaguan
在BASYS3上实现跑马灯的功能。第一LED交替闪烁;第二LED由左至右逐个变亮,再逐个变暗;第三LED由右至左逐个变亮,再逐个变暗;第四LED由两边逐个变亮,再从中间逐个变暗。(Realize the function of the horse light on BASYS3. The first LED flashes alternately; second LED brightens from left to right and then darkens one by one; the third LED turns from right to left, then darkens one by one, and then darkens one by one; fourth LED is brightened by both sides, and then darkening from the middle.)
- 2018-06-21 11:06:16下载
- 积分:1
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dgnszsz
多功能数字钟,在quartusII软件平台上实现的verilog源代码。大家试试看。(Multifunctional digital clock in quartusII software platform to achieve the verilog source code. We try.)
- 2013-09-20 10:20:31下载
- 积分:1
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pci_fpga
对pci9054芯片的配置进行了设置,并对PCI9054的各状态机进行了设置,程序经过了测试(Pci9054 chip on the configuration of the set, and each state machine PCI9054 been set, the program have been tested)
- 2013-10-12 11:39:45下载
- 积分:1
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UART_CESHI
基于VHDL语言的串口发送和接收程序,自己调试通过,并已经运用在工程中(Based on the serial port to send and receive procedures VHDL language, its own debugging, and has been used in the project)
- 2016-08-05 15:27:54下载
- 积分:1
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encode_64_66
自编的64B/66B编码程序,下次上传解码程序。(the 64B/66B coding process is written by myself, i will upload the decoding process next time.)
- 2011-08-27 10:38:53下载
- 积分:1
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iic程序
这是IIc才程序,验证完成,可以直接复用,不许更改,有详细的文档介绍,和对应的代码
- 2022-11-19 11:00:03下载
- 积分:1
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时钟同步的Verilog代码,signal_sync和crossdomain_signal
跨时钟同步功能的Verilog代码,有两个文件,signal_sync和crossdomain_signal
module signal_sync
(
clk_i,
rst_i,
signal_i,
signal_o,
valid_o,
edge_o,
posedge_o,
negedge_o
);
module crossdomain_signal (
input reset,
input clk_b,
input sig_domain_a,
output sig_domain_b
);
- 2022-02-02 17:04:15下载
- 积分:1
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锁相环Verilog代码
锁相环是通信领域最基本的元件,同时在FPGA上也有广泛的应用,本代码是锁相环PLL的Verilog HDL代码,简单易读,能够实现PLL基本的锁相、分频等功能
- 2022-01-26 00:06:30下载
- 积分:1