fpga控制 ad7606 verilog语言

基于Verilog HDL的通信系统设计(Design of communication system based on Verilog HDL)

基于FPGA的AD和DA设计代码及文档(Design code and document of AD and DA based on FPGA)

Interfacing RTC with spartan 3

这个程序为通信中的16QAM调制程序，可用于无线或有线通信系统的调制仿真之用。(The 16QAM modulation communication this program can be used for wireless or wired communication system modulation simulation purposes.)

使用Verilog HDL来控制机器人，六个高精密舵机，舵机运动非常流畅，舵机不抖动(FPGA to control the robot servo, six servos)

a manual for design implementation of fpga and ASIC using verilog

FPGA verilog  的RS232代码， RS232是常用的PC与下位机通信的协议，而FPGA属于可编程器件，在目前的深度学习，机器视觉等领域应用前景十分良好， RS232对于新手FPGA有良好的借鉴作用

驱动8*8点阵块显示汉字，可以自己根据要显示的内容随意更改，已通过验证。(Blocks of 8* 8 dot matrix drive display Chinese characters, you can display the content according to their random changes, has been verified.)

verilogPWM波的设计，属于数字电子技术实验入门的资料

说明：  16位右移位寄存器 下面描述的是一个位宽为16位的右移位寄存器，实际具有环形移位的功能，是在右移位寄存器的基础上将最低位的输出端接到最高位的输入端构成的。其功能为当时钟上升沿到达时，输入信号的最低位移位到最高位，其余各位依次向右移动一位。(16-bit right shift register The following description is a right shift register with a bit width of 16 bits. It actually has the function of circular shift. It is based on the right shift register, which connects the lowest bit output terminal to the highest bit input terminal. Its function is that when the rising edge of the clock arrives, the lowest displacement of the input signal reaches the highest position, and the rest of you move one bit to the right in turn.)