本课件是《自动控制理论基础》这门课程本人多年教学经验的积累，有很高的参考实用价值，属于自动控制理论的精品教学课件。...

本电子数为比较经典的《数据结构及其算法集》，作者为高一凡，比较详细的介绍了各种算法。-In order to compare the electronic digital classic

介绍了自动交换光网络(ASON) 出现的技术背景,并针对ASON的体系结构,着重描述了其具有特色的3 个平面和3 种连接的概念。 然后对ASON所引入的控制平面的功能需求、结构组件、接口模块和信令协议进行了论述。最后,简要介绍了ASON协议的标准化进 程以及ASON在未来光网络中的应用-Introduction of Automatic Switched Optical Network (ASON) technical background, and against the ASON architecture, focusing on description of its unique 3-plane and the concept of three kinds of connections. And then introduced to the ASON control plane functional requirements, structural components, interface modules and signaling protocols are discussed. Finally, a brief introduction of ASON standardization process and the agreement ASON optical network in the future application

jsp编程实例和csdn上几百个问题的解答！对新手很有帮助， -CSDN jsp programming examples and the hundreds of questions! Very helpful for novices,

sun 公司的标准英文教程，配套的源代码。 有练习题，有源代码。如果你想学java，想考java的sun 公司的证书，很有用。-sun" s standard English tutorial, matching the source code. Have exercises, active code. If you want to learn java, want to test the sun" s java certificate, very useful.

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关于FPGA流水线设计的论文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.-FPGA pipelined designs on paper This work invest

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介绍一个基于U S B 2 . 0 接口和D S P 的高速数据采集处理系统的工作原理设计及实现该高速数据 采集处理系统采用TI 公司的TMS320C6000 数字信号处理器和Cypress 公司的USB2.0 接口芯片可 以实现高速采集和实时处理有着广泛的应用前景-based on a U S B 2. 0 S interface and D P high-speed data acquisition and processing system is designed on the principle of the work and the realization of high-speed data acquisition and processing system using TI"s TMS320C6000 digital signal processor and Cypress"s USB 2.0 interface chip can achieve high-speed data acquisition and real-time processing has wide application Prospect

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