JSP图书管理系统

这是一款IEEE14节点的潮流算程序，主要进行潮流计算

手机终端配件进销存源码源码描述：一、源码描述 这是一套手机配件进销存综合管理系统，功能十分的强大，界面非常美观，运营商可直接使用，可以作为二次开发或者毕业设计使用，感兴趣的可以下载看看啊。 二、功能介绍 系统模块： 1、库存管理：终端入库、配件入库、调拨入库、销售出库、调拨出库、退货出库、调拨申请信息、在库维护、业务变更、销售扎帐、报废管理。 2、统计查询：入库查询、调拨查询、销售查询、在库查询、终端查询、退库查询。 3、统计报表：进销存汇总报表、库存周期报表、库存库龄分析报表、库存周转率报表、销售营账统计报表。

该代码是自己通过学习遗传算法编写的小Demo

Verilog的IEEE标准，比较新的一个吧应该是IEEE Std 1364 TM-2005(Revision of IEEE Std 1364-2001)lEE Standard for VerilogHardware Description LanguageSponsorDesign Automation Standards Committeeof theIEEE Computer SocietyAbstract: The Verilog hardware description language(HDL) is defined in this standard. VerilogHDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine-readable and human-readable, it supports the development, verificationsynthesis, and testing of hardware designs; the communication of hardware design data; and themaintenance, modification, and procurement of hardware. The primary audiences for this standardare the implementors of tools supporting the language and advanced users of the languageKeywords: computer, computer languages, digital systems, electronic systems, hardware, hardware description languages, hardware design, HDL, PLI, programming language interface, Verilog,Verilog HDL, verilog PllThe Institute of Electrical and Electronics Engineers, Inc3 Park Avenue. New york. NY 10016-5997 USACopyright@ 2006 by the Institute of Electrical and Electronics Engineers, IncAll rights reserved Published 7 April 2006. Printed in the United states of AmericaIEEE is a registered trademark in the U.S. Patent Trademark Office, owned by the Institute of Electrical and ElectronicsEngineers, IncorporatedVerilog is a registered trademark of Cadence Design Systems, IncPrint:|sBN0-738148504SH95395PDFSBN0-7381-48512SS95395No part of this publication may be reproduced in any form, in an electronic retrieval system or otherwise, without the priorwritten permission of the publisher.IEEE Standards documents are developed within the IEee Societies and the Standards CoordinatingCommittees of the iEEE Standards Association (IEEE-SA)Standards board The ieee develops its standardsthrough a consensus development process, approved by the american National Standards Institute, which bringstogether volunteers representing varied viewpoints and interests to achieve the final product. Volunteers are notnecessarily members of the Institute and serve without compensation. While the ieee administers the processand establishes rules to promote fairness in the consensus development process, the ieee does not independentlyevaluate, test, or verify the accuracy of any of the information contained in its standards.Use of an IEEE Standard is wholly voluntary. The ieee disclaims liability for any personal injury, property orother damage of any nature whatsoever, whether special, indirect, consequential, or compensatory, directly orindirectly resulting from the publication, use of, or reliance upon this, or any other iEEE Standard documentThe ieee does not warrant or represent the accuracy or content of the material contained herein, and expresslydisclaims any express or implied warranTy, including any implied warranty of merchantability or fitness for a specific purpose, or that the use of the material contained herein is free from patent infringement. IEEE Standardsdocuments are supplied "AS IsThe existence of an IEEE Standard does not imply that there are no other ways to produce, test, measurepurchase, market, or provide other goods and services related to the scope of the IEEE Standard. Furthermore, theviewpoint expressed at the time a standard is approved and issued is subject to change brought about throughdevelopments in the state of the art and comments received from users of the standard Every IeeE Standard issubjected to review at least every five years for revision or reaffirmation. When a document is more than fiveyears old and has not been reaffirmed, it is reasonable to conclude Chat ils contents, although still of some valuedo not wholly reflect the present state of the art. Users are cautioned to check to determine that they have thelatest edition of any IEEE StandardIn publishing and making this document available, the IEeE is not suggesting or rendering professional or otherervices for, or on behalf of, any person or entity. Nor is the Ieee undertaking to perform any dutyother person or entity to another. Any person utilizing this, and any other ieee Standards document, should relupon the advice of a competent professional in determining the exercise of reasonable care in any givencircumstancesInterpretations: Occasionally questions may arise regarding the meaning of portions of standards as they relate tospecific applications. When the need for interpretations is brought to the attention of IEEe, the Institute will initiateaction to prepare appropriate responses. Since ifff Standards represent a consensus of concerned interests, it isimportant to ensure that any interpretation has also received the concurrence of a balance of interests. For thisreason, IEEE and the members of its societies and standards coordinating committees are not able to provide aninstant response to interpretation requests except in those cases where the matter has previously received formalconsideration. At lectures, symposia, seminars, or educational courses, an individual presenting information onIEee standards shall make it clear that his or her views should be considered the personal views of that individuarather than the formal position, explanation, or interpretation of the IeeeComments for revision of IEEE Standards are welcome from any interested party, regardless of membership aftil-iation with IEEE. Suggestions for changes in documents should be in the form of a proposed change of texttogether with appropriate supporting comments Comments on standards and requests for interpretations shouldaddressed toIEEE-SA Standards Board445 Hoes lanePiscataway, NJ 08854USANoTE-Attention is called to the possibility that implementation of this standard may require use of subjectmatter covered by patent rights. By publication of this standard, no position is taken with respect to theexistence or validity of any patent rights in connection therewith. The IEf shall not be responsible foridentifying patents for which a license may be required by an ieee standard or for conducting inquiries into thelegal validity or scope of those patents that are brought to its attentionAuthorization to photocopy portions of any individual standard for internal or personal use is granted by the Institute of Electrical and Electronics Engineers, Inc, provided that the appropriate fee is paid to Copyright ClearanceCenter. To arrange for payment of licensing fee, please contact Copyright Clearance Center, Customer Service222 Rosewood Drive, Danvers, MA01923 USA; +19787508400. Permission to photocopy portions of any indi-idual standard for educational classroom use can also be obtained through the Copyright Clearance CenterIntroductionThis introduction is not a part of IEEE Std 1364-2005, IEEE Standard for Verilog Hardware Description LanguageThe Verilog hardware description language(HDL) became an IEEE standard in 1995 as IEEE Std 13641995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in a standardtextual format for a variety of design tools, including verification simulation, timing analysis, test analysisand synthesis. It is because of these rich features that verilog has been accepted to be the language of choiceby an overwhelming number of integrated circuit(IC)designersVerilog contains a rich set of built-in primitives, including logic gates, user-definable primitives, switches,and wired logic. It also has device pin-to-pin delays and timing checks. The mixing of abstract levels isessentially provided by the semantics of two data types: nets and variables. Continuous assignments, inwhich expressions of both variables and nets can continuously drive values onto nets, provide the basicstructural construct. Procedural assignments, in which the results of calculations involving variable and netvalues can be stored into variables, provide the basic behavioral construct. a design consists of a set of modules, each of which has an input/output(1/O)interface, and a description of its function, which can be structural, behavioral, or a mix. These modules are formed into a hierarchy and are interconnected with netsThe Verilog language is extensible via the programming language interface(PLI)and the verilog procedural interface(VPi) routines. The Pli/vPi is a collection of routines that allows foreign functions to accessinformation contained in a Verilog hdl description of the design and facilitates dynamic interaction withsimulation. Applications of PLI/VPI include connecting to a Verilog HDL simulator with other simulationand computer-assisted design(CAD)systems, customized debugging TaskS, delay calculators, andannotatorsThe language that influenced Verilog HDL the most was HILO-2, which was developed at Brunel University in England under a contract to produce a test generation system for the British Ministry of DefensehiLO-2 successfully combined the gate and register transfer levels of abstraction and supported verificationsimulation, timing analysis, fault simulation, and test generationIn 1990, Cadence Design Systems placed the Verilog HDL into the public domain and the independentOpen Verilog International(oVi)was formed to manage and promote Verilog HDL. In 1992, the Board ofDirectors of ovi began an effort to establish Verilog hdl as an ieeE standard. In 1993, the first IEeEworking group was formed; and after 18 months of focused efforts, Verilog became an IEEE standard asIEEE Std 1364-1995After the standardization process was complete, the IEEe P1364 Working Group started looking for feedback from IEEE 1364 users worldwide so the standard could be enhanced and modified accordingly. Thisled to a five-year effort to get a much better Verilog standard in IEEE Std 1364-2001With the completion of IEEE Std 1364-2001, work continued in the larger Verilog community to identifyoutstanding issues with the language as well as ideas for possible enhancements. As Accellera began work-ing on standardizing System Verilog in 2001, additional issues were identified that could possibly have led toincompatibilities between Verilog 1364 and System Verilog. The IEEE P1364 Working group was established as a subcomittee of the System Verilog P1800 Working Group to help ensure consistent resolution ofsuch issues. The result of this collaborative work is this standard ieee Std 1364-2005Copyright C 2006 IEEE. All rights reservedNotice to usersErrataErrata,ifanyforthisandallotherstandardscanbeaccessedatthefollowingurL:http:/stan-dards.ieee.org/reading/ieee/updates/errata/index.html. Users are encouraged to check this URL for errataperiodicaInterpretationsCurrentinterpretationscanbeaccessedatthefollowingUrl:http:/standards.ieeeorg/reading/ieee/interp/Index. htmlPatentsAttention is called to the possibility that implementation of this standard may require use of subject mattercovered by patent rights. By publication of this standard, no position is taken with respect to the existence orvalidity of any patent rights in connection therewith. The IEee shall not be responsible for identifyingpatents or patent applications for which a license may be required to implement an IEEE standard or forconducting inquiries into the legal validity or scope of those patents that are brought to its attentionParticipantsAt the time this standard was completed, the ieee P1364 Working group had the following membershipJohny Srouji, IBM, IEEE SyStem verilog Working Group chairTom Fitzpatrick, Mentor Graphics Corporation, ChairNeil Korpusik, Sun Microsystems, Inc, Co-chairStuart sutherland sutherland hdl inc. editorShalom Bresticker, Intel Corporation, Editor through February 2005The Errata Task Force had the following membershipKaren pynopsys,rKurt baty. WFSDB ConsultinDennis marsa. XilinxStefen Boyd, Boyd TechnologyFrancoise Martinolle, Cadence Design Systems, IncShalom Bresticker, Intel CorporationMike McNamara, Verisity, LtdDennis Brophy, Mentor Graphics CorporationDon Mills, LCDM EngineeringCliff Cummings, Sunburst Design, IncAnders nordstrom, Cadence Design Systems, IncCharles dawson, Cadence Design Systems, IncKaren Pieper, Synopsys, IncTom Fitzpatrick, Mentor Graphics CorpoBrad Pierce, Synopsys, IncRonald goodstein, first shot Logic simulation andSteven Sharp Cadence Design Systems, IncAlec Stanculescu. Fintronic USA IncDesignStuart Sutherland. Sutherland HDL IncMark Hartog, Synopsys incGordon Vreugdenhil, Mentor Graphics CorporationJames Markevitch, Evergreen Technology GroupJason Woolf, Cadence design Systems, IncCopyright C 2006 IEEE. All rights reservedThe behavioral Task Force had the following membership:Steven Sharp, Cadence Design Systems, InC, ChairKurt Baty, WFSDB ConsultingJay lawrence. Cadence design Systems. IncStefen Boyd, Boyd TechnologyFrancoise Martinolle, Cadence Design Systems, IncShalom Bresticker, Intel CorporationKathryn McKinley, Cadence Design Systems, IncDennis brophy, Mentor graphics corporationMichael mcnamara. Verisity LtdCliff Cummings, Sunburst Design, IncDon Mills, LCDM EngineeringSteven Dovich, Cadence Design Systems, IncMehdi Mohtashemi, Synopsys, IncTom Fitzpatrick, Mentor Graphics CorporationKaren Pieper, Synopsys, IncRonald Goodstein, First Shot Logic Simulation andBrad Pierce, Synopsys, IncDesignDave Rich, Mentor Graphics CorporationKeith Gover, Mentor Graphics CorporationSteven Sharp, Cadence Design Systems, IncMark Hartoog, Synopsys, IncAlec Stanculescu. Fintronic USAEnnis Hawk, Jeda TechnologiesStuart Sutherland. Sutherland hdl. IncAtsushi kasuya, Jcda TechnologicsGordon Vrcugdcnhil, Mentor Graphics CorporationThe PLI Task Force had the following membershipCharles Dawson, Cadence Design Systems, Inc, ChairGhassan Khoory, Synopsys, Inc Co-chairTapati Basu, Synopsys, IncMichael rohleder. Freescale Semiconductor. IncSteven Dovich, Cadence Design Systems, IncRob Slater, Freescale Semiconductor IncRalph duncan, Mentor Graphics CorporationJohn Stickley, Mentor Graphics CorporationJim garnett, Mentor Graphics CorporationStuart Sutherland. Sutherland HDL. incJoao geada CLK Design AutomationBassam Tabbara. Novas software. IncAndrzej litwiniuk, Synopsys, IncJim Vellenga, Cadence Design Systems, IncFrancoise Martinolle, Cadence Design Systems, IncDoug Warmke, Mentor Graphics CorporationSachchidananda Patel, Synopsys, IncIn addition, the working group wishes to recognize the substantial efforts of past contributorsMichael McNamara, Cadence Design Systems, Inc1364 Working Group past chair(through September 2004)Alec Stanculescu, Fintronic USA, 1304 Working Group past vice-chair(through June 2004)Stefen Boyd, Boyd Technology, ETF past co-chair(through November 2004)The following members of the entity balloting commitlee voted on this standard. Balloters may have votedfor approval, disapproval, or abstentionAccelleraIntel CorporationBluespec, Inc.Mentor Graphics CorporationCadence Dcsign Systcms, IncSun microsystems, IncIntronic u.s.aSunburst design, IncIBMSutherland hdl lncInfineon TechnologiesSynopsys, IncCopyright C 2006 IEEE. All rights reservedWhen the IEEE-SA Standards Board approved this standard on 8 November 2005, it had the followingmembershipSteve M. mills. chairRichard h. hulett vice chairDon wright Past chairJudith gorman. secretaryMark d. bowmanWilliam B HopfT W. olsenDennis B. BrophyLowell G. JohnsonGlenn parsonsJoseph brudeHerman KochRonald c. petersenRichard coxJoseph L. Koepfinger*Gary s. RobinsonBob davisDavid J lawFrank stoneJulian forster kDaleep c mohlaMalcolm v thadenJoanna n. gueninPaul nikolichRichard l. townsendS. HalpJoe d. watseRaymond hapemanHoward L, wolfmanAlso included are the following nonvoting Ieee-Sa Standards board liaisonsSatish K. aval, NRC RepresentativeRichard Deblasio, DOE RepresentativeAlan H. Cookson, NIST RepresentativeMichelle d, trIEEE Standards Project EditoCopyright C 2006 IEEE. All rights reservedContentsOverview1. 2 Conventions used in this standard1.3SIption1 4 Use of color in this standard1.5 Contents of this standard1.6 Deprecated clauses……….….….….…1.7 Header file listings....18 Examples…………………1.9PNormative references63. Lexical conventions83.1 Lexical tokens3.2 White space3. 3 Comments中··…·········:···············中·····“:·:·:·4·····“··········3. 4 Operators3. 5 Numberssteger constants3.5.2 Real constants123.5.3 Conversion123.6 Strings123.6. 1 String variable declaration133.6.2 String manipulation133.6.3 Special cha3.7 Identifiers. keds, and syste143.7.1 Escaped identifiers143.7.2 Keywords153.7.3 System tasks and functions3.7.4 Compiler directives153.8 Attrib163.8.1 Examples3.8.2 SyIata typ··4.1 Val214.2 Nets and variables4.2.1 Net declarations4.2.2 Variable declarations4.3V4.3.1g v244.3.2 Veclor net accessibility44.4 Strengths4.4.1 Charge strength4.4.2 Drive strength.....卓········中····“·········:·····················:········254.5 Implicit declarations4.6 Net types………264.6.1 Wire and tri nets264.6.2 Wired nets4.6.3TCopyright C 2006 IEEE. All rights reserved4.6.4 Trio and tri l nets4.6.5 Unresolved nets4.6.6 Supply nets324.7 Regs324.8 Integers, reals, times, and realtime4.8.1 Operators and real numbers4.8.2 Conversion4.9 Arrays4.9.1Net arrays…·中·····:··344.9.2 reg and variable arrays344.9.3 Memories4.10 Parameters…………………354.10.1 Module parameters…364.10.2 Local parameters(localparam““374.10.3 Specify parameters……384. Name spaces…39Expressions……5.1 Operators41Operators with real operands425.1.2 Operator precedence………5.1.3 Using integer numbers in expressions…….445.1.4 Expression evaluation order……2451. 5 Arithmetic operators5.1.6 Arithmetic expressions with regs and integers5. 1.7 Relational operators485.1.8Equ495.1.9 Logical operators…495.1.10 bitw isators505.1.11 Reduction operators5.112 Shift operators…….535. 1. 13 Conditional operator535.1. 14 Concatenations545.2 Operands………5.2. 1 Vector bit-Select and part-select addressing..565.2.2 Array and memory addressing.......,.……5.2.3ings585.3 Minimum, typical, and maximum delay expressions5.4 Expression bit lengths5.4.1 Rules for expression bit lengths65.4.2 Examole of expression bit-length problerpl635.4.3 Example of self-determined expressions.645.5 Signed expressions5.5.1 Rules for expression types.....5.5.2 Steps for evaluating5.5.3 Steps for evaluating an assignment5.54 Handling X and Z in signed expressions………5.6 Assignments and truncation6. Assignments……………686.1 Continuous assignments686. 1. 1 The net declaration assignment6.1.2 The continuous assignment statement·····中···:·:·4·中·····6.1.371Copyright C 2006 IEEE. All rights reserved

程序利用了Cat Map来做图像像素位置的置乱，之后再利用Logistic映射来做像素位置的改变。并且还提供计算NPCR与UACI的方法。

提出了一种利用Pareto支配来求解多目标优化问题的自适应和声搜索算法（MOSAHS）。该算法利用外部种群来保存非支配解，为了保持非支配解的多样性，提出了一种基于拥挤度的删除策略，这个策略能较好地度量个体的拥挤程度。用5个标准测试函数对其进行测试，并与其他多目标优化算法相比较。实验结果表明，与其他的算法相比，提出的算法在逼近性和均匀性两方面都有很好的表现，是一种有效的多目标和声搜索算法。102011,47(31)Computer Engineering and Applications计算机工程与应用HMS;(4)和声记忆保留概率HMCR的上下界;(5)音调调节其中,n为所得解的个数,d1为第个解对应目标向量与其最近概率PAR的上下界;(6)最大迭代次数M。的目标向量之间的距离,d为d的平均距离。SP=0表示算步骤2初始化和声记忆库。法所得的解均匀的分布在 Pareto前沿。该指标反映算法所得步骤3产生新解。每次可以通过三种机理产生一个新解分布的均匀程度。解。(1)保留和声记忆库中的分量:(2)随机选择产生;(3)对多样性指标:将算法获得的所有非劣解按某个目标函数(1)、(2)中某些分量进行微调扰动产生。每次产生M个新个体。值的大小有序地分布在目标空间上,h为相邻两点间的距离,步骤4外部种群的更新。从记忆库租新个体中找出非支h为h的平均值,b,b分别为算法获得的边界解与相应极端配解放在外部种群中,计算外部种群的支配关系删除支配解之间的距离,则多样性指标△为解,把非支配解侏留在外部种群中。若外部种群中非支配解的数目超过外部种群规模,则删除多余的个体,每次仅删除hy+h,+∑|h-b(8)个,直到达到外部种群的规模。h,+h1+(n-1h步骤5更新记忆库。计算记忆库和新产生的个体的序极端解指某一目标函数值最大而其他目标函数值最小的并将其按照从大到小的顺序进行排列,前HMS个个体作为新解。n为非劣解的个数。当算法获得的非劣解完全均匀的分的记忆库,进入下一次进化布在均衡面上,h=0,h1=0,所有的h=h,这时△=0。因步骤6判断是否满足终止条件,若满足,则停止迭代,输此,A指标反映非劣解能否均匀的分布在整个均衡面上。出 Pareto最优解集,否则,返回步骤3。4.2数值结果334算法分析为了验证本文提出的算法的有效性,本文采用具有不同由亍和声搜索算法主要是基于邻域搜素的,初始解的好 Pareto前沿的几个典型函数进行仿真实验测试。测试函数坏对搜索的性能影响很大。和声搜索算法可以随机产生初始ZDT1、ZDT2、ZDT3、ZDI4、ZDT6是二维目标函数。由于处理解,也可以通过使用其他的启发式算法或其他方法产生较好多目标优化问题的和声搜索算法还不是很多,所以本文仅与的初始解。和声记忆库HM的大小M是和声搜索算法的种和声搜索算法 IMOHS相比,然后与4种多目标优化算法个重要参数,和声搜索算法之所以具有更强的全局搜索能力,相比,测试结果见表1-表4很大程度上依赖于HM的存在,一般来说,M越大,找到仝局表1MOHS和 MOSAHS的G表2 IMOHS和 MOSAHS的sP最优区域的能力越强。但是随着M的増人,计算量将会变IMOHSMOSAHSIMOHSMOSAHS4大,从而影响到最终搜索到最优解的速度。和声保图概率Dm1781420241-01Dm11433D031.0OE-350100E-0055.3E-36.5328E-004HMCR是和声搜索算法的另一个重要参数,其取值范围是0到5.39-42.1293L-0043.3E-30.0059之间,它决定每次迭代过程中新解产生的方式。在和声搜索ZDT2ZDT224E-48.8573E-0052.4E-35.9104E-004算法中,因新解产生时每个变量都依赖于HMCR,故HMCRDT39.80E-465670E-004ZDT32.|B-20.0077应取较大的值,通常HMCR的值在0.8到1.0之间。音调调节1.7OE-324699E-00529E-28.5088E-004率PAR在和声搜索中起控制局部搜索的作用,它可使搜索逃表3儿种多目标优化算法的GD离局部最优,其值一般取0.1到0.5之间。NSGA-IISPEA2MOPSOIOSADE MOSAHS1.3437E-33.8175E-31.8564E-11.2485E-329624EZITI14078E-449142E-37.7429E-297574E-550100E-0054数值实验9.8112E-48.6104E-352428E-19.8051E-42.1293E-004ZDT241算法性能的评价指标6.4138E-42.5973E-32.9699E-149107E-58.8573E-005多目标优化问题的解质量评价主要集中在所求得的解与2.4783E-397165E-34.3418E-2.1620E-36.5670E-004ZDT31.2746F-45.2305F-364880E-219962F-42.4699E-005理论最优值之间的差距,以及求得的解的分散程度和多样性,5.1635E-29.2512E12010E-349244E-004这里采用由 Van veldhuizen和 Lamont在1998年提出来的世ZDT413281E-34.282lE-18.3745E-549411E-005代距离( Generational Distance,GD)来衡量所求解与理论解75-21.909-252103E-22656-31190-004ZDT6之间的差距,世代距离被定义为如下形式:60797E-31.3994E-32.4963E-21.0967E-48.0065E-006表4儿种多目标优化算法的AGD=NSGA-IISPEA2MOPSO MOSADE MOSAHS0.504290.296440.2038050.131950.4063其中,n为最优解数目,d,为所求得第i个个体在目标空间与理ZDTI3.9251E-21.0850E-116956E-25.692lE-300219论 Pareto最优前沿的最小欧氏距离。世代距离GD越小,算法0.487750.505170.2880260.120990.3764ZDT2逼近 Pareto最优解集的程度越妤,当所得到的解刚好和从最优2.7686E-21.8356E-11.7580E-279444E-300359前端取得的点重合时,GD=0。0.590250.503100.6177960.437830.6388ZDT33.0439E-29.7283E-23.5019E-28.0801E-300103解的分散程度用下式来度量0.375240.727660.3235490.118270441ZDT42.4448E-25.515-13.2953E-25.869E-30.0227SP=n-/~(d-d1)0.486ll0.296441.1232580.1331904325(7)ZDT63.6054E-21.0850E-11.731E-19.8303E-300363InInj∈(1,n)②/(x)-/1(),=1,2,…,n,i≠其中表1、表2中MOHS算法的数据来源于文献5],和o1994-2012ChinaAcademicJournalElectronicPublishingHouse.Allrightsreservedhttp://www.cnki.net陈莹珍,高岳林:多目标自适应和声搜索算法2011,47(31)0.900.80.80.60.70.70.40.60.60.20.30.20.40.10.10.800.10.20.30.40.50.60.70.80.91.000.10.20.3040.50.60.70.80.91.000.10.20.30.40.50.60.70.80.9图1ZDT1图2ZDT2图3ZDT3声记忆库的规模为10,和声保留概率的上下界HMCR==0.95,5总结HMCR=0.85,音调调节概率的上下界PAR、=0.2,PAR=本文将和声搜索算法应用于多目标优化问题的求解,提0.15,最大迭代次数为1000.为了消除实验中的随机性,并进出了一种新的基于拥挤度的多目标和声搜索算法 MOSAHS。行算法性能指标评价,对每个测试函数均重复计算10次。表3、该算法利用单个解与解之间的距离以及单个解与整体解之间表4中 NSGA-II,SPEA2, MOPSO, MOSADE的数据,来源于文的距离,删除种群中的个体,并利用序来更新和声记忆库。数献[161。对丁本文提出的多目标和声搜素算法 MOSAHS,和值实验数据表明,提出的算法在逼近性和多样性两方面都有声保留概率的上下界分别为095085,音调调节概率的上下界很好的表现是一种有效的多目标和声搜索算法。然而,和声分别为0.2、0.15,和声记忆库的规模为10,外部种群的规模为搜索算法和其他群智能算法一样,收敛性的理论证明很困难100,最大迭代次数为10000,算法运行10次。有待进一步的深入研究。表1中上行表示算法收敛度指标GD的平均值,下行表示GiD的标准方差;表2中上行表示分散度指标SP的平均值,下参考文献:行表示SP的标准方差;表3中上行表示算法收敛度指标GD的 Schaffer J D Multiple objective optimization with vector evaluat-平均值,下行表示GD的标准方差;表4中上行表示多样性指ed genetic algorithms[C]//Proceedings of the lst IEEE International Conference on Genetic Algorithms. Lawrence Erlbaum标Δ的平均值,下行表示多样性指标△的标准方差。1985:93-100从表1、表2可以看出本文提出的算法 MOSAHS在收敛(2]HomJ, Nafpliotis N, Goldberg D E A niched Pareto genetic al度和分散度上均优于 IMOHS;从表3、表4可以看出,与NSgorithm for multi-objective optimization[C],Proceedings of thGA- SPEA2、 MOPSO、 MOSADE算法相比,本文提出算法Ist IEEE Conference on Evolutionary Computation, PiscatawMOSAHS的收敛性优于前面四种算法,在多样性方面,与NS994.1:82-87GA- I SPEA2算法相当,此 MOPSO、 MOSADE算法稍差。[3] Srinivas N, Deb KMulti-objective function optimization using图1~图5是本文提出的算法( MOSAHS)对ZDT1,ZDT2non-dominated sorting genetic algorithms[J]. Evolutionary CompuZDT3,ZDT4,ZDT6的函数图像。tation,l994,2(3):221-248[4] Deb K, Pratap A, Agarwal S, et al. A fast and elitist multi-objective genetic algorithm: NSGA-IIJ.IEEE Transactions on Evolu0.8tionary Computation, 2002, 6(2): 182-1970.7[5] Zitzlcr E, Thiclc L Multi-objcctivc evolutionary algorithms: a0.6comparative case study and the strength parel approach0.5IEEE Transactions on Evolutionary Computation, 1999, 3(4)0.40.2[6 Zitzler E, Thiele L SPEA2: improving the strength pareto evolu-0.1ionary algorithm for multi-objcctivc optimization[R].Rcscarch00.10.20.3040.50.60.7080.91.0JrL,2001[7 Knowles J, Corne D The pareto archived evolutionary strategy图4ZDT4A new baseline algorithm for multi-objective optimization[C]//1.0Proceedings of the Conference on Evolutionary Computation Pis-0.9ltaway, NJ: IEEE Press, 1999: 98-10508[8] Tsai S J, Sun T Y, Liu CC, et al. An improved multi-objparticle swarm optimizer for multi-objective problems[J]. ExpertSystems with Applications, 2010, 18(2): 1-150.4[9 Geem Z W, Kim J H, Loganathan G V.A new heuristic optimi-0.zation algorithm: Harmony scarch[J]. Simulation, 2001, 76(2): 60-80[10] Mahdavi M, Fesanghary M, DaInangir E An improved harmony0.20.30.40.50.60.70.80.91.0search algorithm for solving optimization problem] AppliedfMathematics and Computation, 2007, 188(2): 1567-1597图5ZDT6(下转174页o1994-2012ChinaAcademicJournalElectronicPublishingHouse.Allrightsreservedhttp://www.cnki.net1742011,47(31)Computer Engineering and Applications计算机工程与应用插值算法对(a)放大3×3倍后的效果图;图6〔g)是采用本文中个像素需24位。在实现本文算法时,需在读取位图文件信息的插值算法对(a)放大3×3倍后的效果图,其中(a-b-1/6,头时进行判断是属哪类图像(灰度/24真彩色),对于灰色图像1=2=15°)。图7(a)是256×256的原始图像,(b)为原图经只需对图像进行逐像素(也即逐字节)的处理即可。而对于24降采样生成的128×128的缩小图像;(c)、(d为分别采用最邻位彩色图像则分别对每一像素中的3个分量分别处理即可,所近插值、双线性插值算法对(b)放大2×2倍后的效果图。(e)是得到的结果与灰度图是一致的,如图8所示。(b)用 Prewitt算子检测到的图像边缘效果图,(f)是采用本文提出的插值算法对(b)放大2×2倍后的效果图,其中(a=b=1/4,q1=92=15°)。从灰度值显示及图像效果可以看出本文所提出的算法在一定程度上突出了边缘,并修复了部分断裂的边缘,图6(d)中的像素灰度值显示当放大倍数为2×2时,修复边缘的效果更加显著。(a)原图(b)双线性插(c)本文算法(2×2)值(2×2)(a=b=16,1=2=15°)图8采用不同插值算法放大的图像效果图5结论基于图像边缘信息的双线性插值算法充分利用了图像的(a)原图(b)原图降采样(c)最邻近插边缘信息对放大图像边缘上的插值点及边缘邻接点做了较好值法(2×2)的插值处理,这种处理方式使放大后的图像在很大程度上保护了图像的细节,较其他插值算法简单且效果明显,更优于传统双线性插值算法。(d)双线性(e)用 Prewitt算(f)本文算法(2×2)参考文献:插值(2×2)子检测到的边缘(a=b=14,91=中2=15[] Castleman K R数字图象处理[M]北京:清华大学出版社,202图7采用不同插值算法放大的图像效果图117-119[2]孙成叶,桑农图像双线性插值无级放大及其运算量分析[计算上述实验采用的是8位的灰度图像,其实本文所提出的算机工程,2005,31(9:167-169法同样适用于彩色图像,尤其是24位的真彩色图像。灰度图[3]谢美华,王正明基于图像梯度信息的插值方法中国图象图形像的存储文件带有图像颜色表,此颜色表共有256项,图像颜学报,2005,10(7):856-861色表中每一项由红、绿、蓝颜色分量组成,且红、绿、蓝的颜色4Liⅹi, Orchard M T New edge-direcled inlerpolalionJJIEEE分量值都相等。而且,灰度图像的每个像素由8位组成,其值Transactions on Image Processing, 2001, 10(10): 1521-1527范围从0到25,表示256种不同的灰度级,每个像素的像素值5岁立摩,杨勋年基于细分的图像抽值算法门计算机轴助设计与是图像颜色表的表项入∏地址。对于彩色图像而言,若是伪图形学学报,2006,18(9):1311316.彩色图像,则其与灰度图像相似,其存储文件中也带有图像颜孟晋字,华思基于形状的二维灰度图象插值门中国图象图形色表,整幅图像也仅有256种颜色,每个像素由8位组成,但在学报,2003,3(3):312-316图像颜色表中的红、绿、蓝颜色分量不全相等,此时,每个像素I] Yang Xunnian Normal based subdivision scheme for curve design[J]. Computer Aided Geometric Design, 2006, 23(3): 243-260的像素值不是出每个基色分量的数值决定,而是把像素值当s]杨淑莹vC+图像处理程序设计M2版北京:清华大学出版社做图像颜色表的表项入口地址。而24位的真彩色图像的存储2005:130-132文件中则不带有图像颜色表,图像中每一像素是由RGB三个19G0 nzalez r o. Woods e数字图像处理M2版北京:电子1分量组成,每个分量各占8位,每个分量的取值是0到255,每业出版社,2009:463-471上接111页)[15 van Veldhuizen D A, Lamont G B Evolutionary computation[11] Kang S L, Geen Z W.A new structural optimization methodand convergence to a Pareto front[C]/Koza J R Late Breakbased on the harmony search algorithm[J]. Comput Struct, 2004ing Papers at the genetic Programming Conference, Stanford82(9/10):781-798University, California, Stanford Bookstore, 1998: 221-228[12] Geem Z W. Optimal cost design of water distribution networks[l6]刘思远,刘景青.一种新的多目标改进和声搜索优化算法门计算using harmony search[J].Eng Optimiz, 2006, 38(3): 259-280机工程与应用,2010,46(34):27-30[131 Deb K Multi-objective optimization using evolutionary algorithm(M. [17] Wang Yaonan, Wu Lianghong, Yuan Xiaofang. Multi-objectiveChichester: lohn Wiley&Sons, 2001self-adaptive differential evolution with elitist archive and[14]陈莹珍,高岳林混沌自适应和声搜索算法太原理工大学学crowding entropy-based diversity measure[J]. Soft Compute报,2011,42(2):141-1442010:193-209o1994-2012ChinaAcademicJournalElectronicPublishingHouse.Allrightsreservedhttp://www.cnki.net

用C语言实现了直方图均衡化，内有测试图片。非常好用。

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2019年5月软考高项信息系统项目管理，马军（小马老师）VIP课程题目书（05-18年真题，论文）pdf,总共1450页，货真价实，现在分享出来，希望大家一起考过！！！

halcon软件中模板定位的相关原理介绍，由于是专利，所以讲的比较细，每个部分都会有比较详细的介绍，有做视觉定位的开发人员，建议好好研究一下。