基于PLC和组态王的温度控制系统设计完整毕业论文
基于PLC和组态王的温度控制系统设计完整毕业论文日录第一章前言…1.1项日背景、意义1.2温控系统的现状1.3项目研究内容…第二章PLC和HM工基础……..2.1可编程控制器其础2.1.1可编程訇器的产生和应用………2.1.2可编程制器的组成和工作原理……2.1.3可编程控制器的分类及特点.2人机界面基础..2.2.1人机界面的定义……2.2.2人机界面产品的组成及工作原理889922.3人机界面产品的特点…第三章PLC控制系统硬件设计中审…103.1PLC控制系統设计的基本原则和步骤3.1.1PLC控制系统设计的基本原则103.1.2PLC控制系统设计的一般步骤.…111-111111132PLC的选型与砭件配置….…133.2.1PC型号的选择3.2.2S7-200CPU的近择143.2.3EM231模拟量输入模坎…1432.4热电式传感器1633I/O点分及电气连接图173.4PC控制器的设计173.4.1控制系统数学模型的建立……173.4.2PID控制及参数整定…19第四章PLC控制系统软件设计…4.1PLC程序设计方法·=·“““:·····““·:··“:4*·:::·ss·s····4.2编程钦件STEP7-- MICRO/WIN模述4.2.1STEP7- Micro/W|N简单介绍234.2.2梯形图语言特点,4.2.3STEP7- Micra/WN参数设置(通讯设置)54.3程序设计274.3.1设计思路274.3.2控制程斥流程图..……274.3.3梯形图程序.284.34PID指令向导的运用4.3.5语句表(STL)程序35第五章基于组态王的HMI设计…5.1人机界面(HMI)设计375.1.1监控主界面量++·++++分什分++f++b世+,."+++子量++-晋++++出±“++++““++世“+++++++牙++土++量世““++世世385.1.2实时趋势由线…395.1.3历史趋势曲线!1:1t!405.1.4报警窗一5.1.5设定画面5.2变量以置425.3动画连接…第六章系统运行结果及分析……466.1系统运行….466.2运行结果分析…476.2.1温度趋势曲线分析……47622报警信息分析…49第七章总结香音看量音重量重量套音音音音音量量音音音音盘量晋牙量雷看宙曲连自尝普套套50参考文献…5致谢·…如一哪物物自回.错误!木定义书签第一章前言1.1项目背景、意义温度控制在电子、冶金、机械等工业领域应用非常广泛。由于其具有工况复杂、参效多变、运行惯性大、控制滞后等特点,它对控制调节器要求极高。目前,仍有相当部分工业企业在用窑、炉等烘千生产线,存在着控制精度不高、炉内温度均匀性差等问题,达不到工艺要求,造成装备运行成木费用高,产出品品质低下,严重影响企业经济效益,急需技术改造近年来,国内外对温度控制器的研究进行了广泛、深入的研究,特别是随着计算机技术的发展,温度控制器的研究取得了巨大的发展,形成了一批商品化的温度调节器,如:职能化PID、模糊控制、臼适应控制等,其性能、控制效果好,可广泛应用于温度控制系统及企业相关设备的技术改造服务。在工业自动化领域内,PLC(可编程控制器)以其可靠性高、抗干扰能力强编程简单、功能强大、性价比高、体积小、能耗低等显著特点广泛应用于现代工业的自动控制之中,目前的工业控制中,常常选用PLC作为现场的控制设备,用于薮据采集与处理、逻辑判断、输出控制;而上位机则是利用HI软件来完成工业控制状态、流程和参数的显示,实现监控、管理、分忻和存储等功能。这种监控系统充分利用了PLC和计算机各自的特点,得到了广泛的应用。在这种方式的基础上设计了一套温度控制系统。以基于PC的下位机和完成IMI功能的上位杌相结合,构建成分布式控制系统,实现了浧度自动控制。PLC不仅具有传统继电器控制系统的控制功能,而且能扩展输入输岀模块,特别是可以扩展一些智能控制模块,构成不同的控制系统,将模拟量输λ输岀控制和现代控制方法融为一体,实现智能控制、闭环控制、多控訇功能一体的综合控制。现代PC以集成度皛、功能强、抗干扰能力强、组态灵活、⊥作稳定受到普遍欢迎,在传统工业的现代化改造中发挥越来越重妟的作用,尤其逅合温度控制的要求此外,随着Tν自动化水平的迅速提高,用户对控制系统的过程监控要求越来越高,人机界面(HMⅠ的出现正好满足了用户这一求ε人机界面可以对控制系统进行全面睑控,包括参薮监测、信息处理、在线优化、报警提示、数据记录等功能,从而使控制系统变得简单易懂、搀作人性化,深受广大用户的喜欢。人机界面(HMI)在自动控制领域的作用日益显著。HM正在成为引导工业生产制造走向成功的重要因素,因为这些系统越来越多的用于监控生产过程,让过程变得更加准确、简洁和快速。HMI其实广义的解释就是“使用者与机器间沟通、传达及接收信息的一个接口”。举个例子来说,在一座工厂里头,我们要搜集工厂各个区域的温度、湿度以及工厂中机器的状态等等的信息透过一台主控器监视并记录这些参数,并在一些意外状况发生的时候能够加以处理。这便是一个很典型的 SCADA/HMI的运用,一般而言,HI系统必须有几项基本的能力:实吋的资料趋势显示——把撷取的资料立即显示在屏幕上。白动记录资料——自动将资料储存至数据库中,以便日后査看历史资料趋势显示—把数据库中的资料作可视化的旱现报表的产生与打印——能把资料转换成报表的格式,并能够打印出来。图形接口控制操作者能够透过图形接口直接控制机台等装置。警报的产生与记录—使用者可以定义一些警报产生的条件。比方说温度过度或压力超过临界值,在这样的条件下系统公产生警报,通知作业员处理。1.2温控系统的现状自70年代以来,由于工业过程控制的需要,特别是在微电子技术和计算机技术的迅猛发展以及自动控制理论和设计方法发晨的推动下,国内外温度控制系统发展迅速,并在职能化、自适应、参数自整定等方面取得成果,在这方面,以日本、美国、德国、瑞典等国技术领先,都生产山了“批商品化的、性能优异的温度控制器及仪器仪表,并在各行各业广泛应用凹。它们主要具有如下特点:1)适应于大惯性、大滞后等复杂温度控制系统的控制。2)能适应于受控系统数学模型难以建立的温度控制系统的控制。3)能适应于受控系统过程复杂、参数时变的温度控制系统的控制。4这些温度控制系统普遍采用自遹应控制、自校正控制、模糊控制、人工职能等理论及计算机技术,运用先进的算法,适应的范围广泛。5)温度控制器旾遍具有参数自整定功能。借助计算杌软件技八,温控器具有对控制参数及特性进行自动整定的功能。有的还具有自学习功能,它能够根据历史经验炇控制对象的变化情况,自动调整相关控制参数,以保证控制效果的最优化。6)温度控系统既冇控制精度高、抗干扰能υ强、鲁棒性好的特点。目前,国外温度控制系统及仪表正朝着高精度、智能话、小型化等方面快速发展l温度控制系统在国内各行各业的应用虽然已经十分广泛,但从国内生产的温度控制器来讲,总体发展水平仍然不高,同日本、美国、德国等先进国家相比仍然有着较大的差距。目前,我国在这方面总体水平处于20世纪80年代中后期水平,成熟产品主要以“点位”控制及常规的PID控制器为主,它只能适应一般温度系统控制,难于控制滞后、复杂,时变温度系统控制。而适应于较髙控制场合的智能化、自适应控制仪表,国内技术还不十分成熟。形成商品化并在仪表控制参数的自整定方面,国外已有较多的成熟产品,但由丁国外技术保密及我国开发工作的滞后,还没开发出性能可靠的自整定软件。控制参数大多靠人工经验及我国现场调试来确定。这些差距,是我们必须努力克服的。随着我国加入WTO,我国政府及企业对此非常重视,对相关企业资源进行了重组,相继建立了一些国家、企业的研发中心,并通过合资、技术合作等方式,组建了一批合资、合作及独资企业,使我国温度仪表等工业得到迅速的发展。随着科学技术的不断发展,人们对温度控制系统的要求愈来愈高,因此,高精度、智能化、人性化的温度控制系统是国內外必然发展趋势1.3项目研究内容可编程控制器(PLC)是集计算机技术、自动控制技术和通信技术为一体的新型自动控制装置。其性能优越,已被广泛应用于工业控制的各亼领域,并已成为工业自动化的三大支柱(PLC、工业机器人, CAD/CAM之。PLC的应用己成为·个世界潮流,在不久的将米PC技术在我国将得到更全面的推和应用。本论文研究的是PLC技术在温度监控系统上的应用。从整体上分析和研究了控制系统的硬件配置、电路图的设训、程序设讣,控淛对黎效芓模型的建立、控制算法的选择和参数的整定,人机界面的设计等。本论文通过德国西门子公司的S7-200系列PC控制器,温度传感器将检测到的实际炉温转化为电压信号,经过模拟量输入模块转换成数字星信号并送到PLC中进行PI调节,PID控制器输出量转化成占空比,通过同态缢电器控制炉子加热的通断来实现对炉子温度的控制。同时利用平控公司的组态软件“组态王”设计一个人机界面(HMⅠ),通过串行口与可编程控制器通信,对控訇系统进行全面监控,从而使用户操作更方便。总体上包括的技术路线:硬件设计,软件编程,参数整定等。全论文分七章,各章的主要内容说明如下。第一章,对温度控制系统应用的背景及国内外的发展状况进行了阐述,指出了本文的研究意义所在。第二章,简单概述了PLC和人杌界面的基本概念以及结构功能等基础内容。第三章,主要从系统没计结构和硬件设计角度,介绍该项目的PLC控制系统设计步骤、PLC的硬件配置、妒部电路设计以及PLC控制器的设计和参数的整第四章,在硬件设计的基础上,详细介绍了本项目软件设计,主要包括软件设计的基本步骤、方法,编程软件STE7- Micro/WIN的介绍以及本项目稈序设第五章.详细介绍了如何在亚控公司的组态软件“组态王”的基础上进行人札界面的设计。第六章,展示了系统运行结果,然后对其分析得出结论。第七章,总结全文第二章PLC和HMI基础可编程逻辑控制器是一种工业控制计算机,简称PLC( Programmable logicController),它使用了可编程序的记忆以存储指令,用来执行诸如逻辑、顺序、计时、计数和演算等功能,并通过数字或模拟的输入和输出,以控制各种机械或生产过程。2.1可编程控制器基础2.1.1可编程控制器的产生和应用20世纪60年代,计算机技术开始应用于⊥业领域,由于价格高、输入电路不匹配、编程难度大以及难于适应恶劣工业环堉等原因,未能在工业控制领域获得推广。1968年,美国通用汽车公司(GM)为了适应产工艺不断更新的需要,要求寻找一种比继电器更可靠、功能史齐全、响应速度更快的新型下业控制器,并从用户角度提出了新一代控制器应具备的十大条件,立即引发了开发热潮。1969年美国数字设备公司(DFC)根据美国通用汽车公司的这种要求,研制成功了世界上第一台可编程控制器,并在通用汽车公司的自动装配线上试用,取得很好的效果。从此这项技术迅速发展起来。随着PLC功能的不断完善,性价比的不断提高,PLC的应用面也越来越广。目前,PLC在国内外已经广泛应用于铟铁、石油、化工、电力、建材、机械制造、汽车、轻纺、交通运输、环保及文化娱乐等各个行业。PC的应用范围通常可分为厂关逻辑控制、运动控制、过程控制、机楲加工中的欻字控制、机器人控制、通信和联网等52.1.2可编程控制器的组成和工作原理PLC从组成形式上一般分为整体式和模块式两种,但在逻辑结构上基本相同。无论是整体式还是模块式,从硬件结构看,PLC都是由CP、存储器、L/0接口单汇攴扩展接口和扩展部件、外设接口歧外设和电涼等部分组成,各部分之间通过系统总线连接。PLC的基本结构如图2-1所示:存储单元中央处理单元输入接CPU输出接电源图21PLC基本结构图1)CPU(中央处理器)CPU是PLC的核心,由运算器、控制器、寄存器、系统总线,外围芯片、总线接口及有关电路构成。它的功能是接收并存贮用户程序和数据,用扫描的方式采集由现场输入装置送来的状态或数据,并存入规定的备存器中,同时,诊断电源和PLC内部电路的工作状态和编程过程中的语法错误等,是PC不可缺少的组成单元。主要功能包括以下几个方面。1)接收从编程器或者计算机输入的程序和薮据,并送入用户程序存储器存储(2)监视电源、FLC内部各个单元电路的工作状态。3〕诊断编程过程中的语法错淏,对用户程序进行编译。(4)在PC进入运行状态后,从用户程序存储器中逐条读取指令,并分析、执行该指令(5)采集由现场输入装置送来的数据,并存入指定的寄存器口6)按稈斥进行处珅,根椐运算结果,更新有关标志位的状态和输岀状态或数据寄存器的内容。(7)根据输岀状态或数据寄存器的有关内容,将结果送到输岀接口。8)响应中断和各种外围设备(如编程器、打印机等)的任务处理谓求。2)1/接口∏LC是通过各种I/O接口模块与外界联系的,按Ⅰ0点数确定模块规格及数量,I0模块可多可少,但其最大数受CFU所能管理的基本配置能力的限制,即受最大的底板或机架糟数限制。I/O嫫块集成了PC的I/电路,其输入暂存器
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Verilog-IEEE Std 1364 -2005 IEEE Standard
Verilog的IEEE标准，比较新的一个吧应该是IEEE Std 1364 TM-2005(Revision of IEEE Std 1364-2001)lEE Standard for VerilogHardware Description LanguageSponsorDesign Automation Standards Committeeof theIEEE Computer SocietyAbstract: The Verilog hardware description language(HDL) is defined in this standard. VerilogHDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine-readable and human-readable, it supports the development, verificationsynthesis, and testing of hardware designs; the communication of hardware design data; and themaintenance, modification, and procurement of hardware. The primary audiences for this standardare the implementors of tools supporting the language and advanced users of the languageKeywords: computer, computer languages, digital systems, electronic systems, hardware, hardware description languages, hardware design, HDL, PLI, programming language interface, Verilog,Verilog HDL, verilog PllThe Institute of Electrical and Electronics Engineers, Inc3 Park Avenue. New york. NY 10016-5997 USACopyright@ 2006 by the Institute of Electrical and Electronics Engineers, IncAll rights reserved Published 7 April 2006. Printed in the United states of AmericaIEEE is a registered trademark in the U.S. Patent Trademark Office, owned by the Institute of Electrical and ElectronicsEngineers, IncorporatedVerilog is a registered trademark of Cadence Design Systems, IncPrint:|sBN0-738148504SH95395PDFSBN0-7381-48512SS95395No part of this publication may be reproduced in any form, in an electronic retrieval system or otherwise, without the priorwritten permission of the publisher.IEEE Standards documents are developed within the IEee Societies and the Standards CoordinatingCommittees of the iEEE Standards Association (IEEE-SA)Standards board The ieee develops its standardsthrough a consensus development process, approved by the american National Standards Institute, which bringstogether volunteers representing varied viewpoints and interests to achieve the final product. Volunteers are notnecessarily members of the Institute and serve without compensation. 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IEEE Standardsdocuments are supplied "AS IsThe existence of an IEEE Standard does not imply that there are no other ways to produce, test, measurepurchase, market, or provide other goods and services related to the scope of the IEEE Standard. Furthermore, theviewpoint expressed at the time a standard is approved and issued is subject to change brought about throughdevelopments in the state of the art and comments received from users of the standard Every IeeE Standard issubjected to review at least every five years for revision or reaffirmation. When a document is more than fiveyears old and has not been reaffirmed, it is reasonable to conclude Chat ils contents, although still of some valuedo not wholly reflect the present state of the art. Users are cautioned to check to determine that they have thelatest edition of any IEEE StandardIn publishing and making this document available, the IEeE is not suggesting or rendering professional or otherervices for, or on behalf of, any person or entity. Nor is the Ieee undertaking to perform any dutyother person or entity to another. Any person utilizing this, and any other ieee Standards document, should relupon the advice of a competent professional in determining the exercise of reasonable care in any givencircumstancesInterpretations: Occasionally questions may arise regarding the meaning of portions of standards as they relate tospecific applications. When the need for interpretations is brought to the attention of IEEe, the Institute will initiateaction to prepare appropriate responses. Since ifff Standards represent a consensus of concerned interests, it isimportant to ensure that any interpretation has also received the concurrence of a balance of interests. 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Suggestions for changes in documents should be in the form of a proposed change of texttogether with appropriate supporting comments Comments on standards and requests for interpretations shouldaddressed toIEEE-SA Standards Board445 Hoes lanePiscataway, NJ 08854USANoTE-Attention is called to the possibility that implementation of this standard may require use of subjectmatter covered by patent rights. By publication of this standard, no position is taken with respect to theexistence or validity of any patent rights in connection therewith. The IEf shall not be responsible foridentifying patents for which a license may be required by an ieee standard or for conducting inquiries into thelegal validity or scope of those patents that are brought to its attentionAuthorization to photocopy portions of any individual standard for internal or personal use is granted by the Institute of Electrical and Electronics Engineers, Inc, provided that the appropriate fee is paid to Copyright ClearanceCenter. To arrange for payment of licensing fee, please contact Copyright Clearance Center, Customer Service222 Rosewood Drive, Danvers, MA01923 USA; +19787508400. Permission to photocopy portions of any indi-idual standard for educational classroom use can also be obtained through the Copyright Clearance CenterIntroductionThis introduction is not a part of IEEE Std 1364-2005, IEEE Standard for Verilog Hardware Description LanguageThe Verilog hardware description language(HDL) became an IEEE standard in 1995 as IEEE Std 13641995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in a standardtextual format for a variety of design tools, including verification simulation, timing analysis, test analysisand synthesis. It is because of these rich features that verilog has been accepted to be the language of choiceby an overwhelming number of integrated circuit(IC)designersVerilog contains a rich set of built-in primitives, including logic gates, user-definable primitives, switches,and wired logic. It also has device pin-to-pin delays and timing checks. The mixing of abstract levels isessentially provided by the semantics of two data types: nets and variables. Continuous assignments, inwhich expressions of both variables and nets can continuously drive values onto nets, provide the basicstructural construct. Procedural assignments, in which the results of calculations involving variable and netvalues can be stored into variables, provide the basic behavioral construct. a design consists of a set of modules, each of which has an input/output(1/O)interface, and a description of its function, which can be structural, behavioral, or a mix. These modules are formed into a hierarchy and are interconnected with netsThe Verilog language is extensible via the programming language interface(PLI)and the verilog procedural interface(VPi) routines. The Pli/vPi is a collection of routines that allows foreign functions to accessinformation contained in a Verilog hdl description of the design and facilitates dynamic interaction withsimulation. Applications of PLI/VPI include connecting to a Verilog HDL simulator with other simulationand computer-assisted design(CAD)systems, customized debugging TaskS, delay calculators, andannotatorsThe language that influenced Verilog HDL the most was HILO-2, which was developed at Brunel University in England under a contract to produce a test generation system for the British Ministry of DefensehiLO-2 successfully combined the gate and register transfer levels of abstraction and supported verificationsimulation, timing analysis, fault simulation, and test generationIn 1990, Cadence Design Systems placed the Verilog HDL into the public domain and the independentOpen Verilog International(oVi)was formed to manage and promote Verilog HDL. In 1992, the Board ofDirectors of ovi began an effort to establish Verilog hdl as an ieeE standard. In 1993, the first IEeEworking group was formed; and after 18 months of focused efforts, Verilog became an IEEE standard asIEEE Std 1364-1995After the standardization process was complete, the IEEe P1364 Working Group started looking for feedback from IEEE 1364 users worldwide so the standard could be enhanced and modified accordingly. Thisled to a five-year effort to get a much better Verilog standard in IEEE Std 1364-2001With the completion of IEEE Std 1364-2001, work continued in the larger Verilog community to identifyoutstanding issues with the language as well as ideas for possible enhancements. As Accellera began work-ing on standardizing System Verilog in 2001, additional issues were identified that could possibly have led toincompatibilities between Verilog 1364 and System Verilog. The IEEE P1364 Working group was established as a subcomittee of the System Verilog P1800 Working Group to help ensure consistent resolution ofsuch issues. The result of this collaborative work is this standard ieee Std 1364-2005Copyright C 2006 IEEE. All rights reservedNotice to usersErrataErrata,ifanyforthisandallotherstandardscanbeaccessedatthefollowingurL:http:/stan-dards.ieee.org/reading/ieee/updates/errata/index.html. Users are encouraged to check this URL for errataperiodicaInterpretationsCurrentinterpretationscanbeaccessedatthefollowingUrl:http:/standards.ieeeorg/reading/ieee/interp/Index. htmlPatentsAttention is called to the possibility that implementation of this standard may require use of subject mattercovered by patent rights. By publication of this standard, no position is taken with respect to the existence orvalidity of any patent rights in connection therewith. The IEee shall not be responsible for identifyingpatents or patent applications for which a license may be required to implement an IEEE standard or forconducting inquiries into the legal validity or scope of those patents that are brought to its attentionParticipantsAt the time this standard was completed, the ieee P1364 Working group had the following membershipJohny Srouji, IBM, IEEE SyStem verilog Working Group chairTom Fitzpatrick, Mentor Graphics Corporation, ChairNeil Korpusik, Sun Microsystems, Inc, Co-chairStuart sutherland sutherland hdl inc. editorShalom Bresticker, Intel Corporation, Editor through February 2005The Errata Task Force had the following membershipKaren pynopsys,rKurt baty. WFSDB ConsultinDennis marsa. XilinxStefen Boyd, Boyd TechnologyFrancoise Martinolle, Cadence Design Systems, IncShalom Bresticker, Intel CorporationMike McNamara, Verisity, LtdDennis Brophy, Mentor Graphics CorporationDon Mills, LCDM EngineeringCliff Cummings, Sunburst Design, IncAnders nordstrom, Cadence Design Systems, IncCharles dawson, Cadence Design Systems, IncKaren Pieper, Synopsys, IncTom Fitzpatrick, Mentor Graphics CorpoBrad Pierce, Synopsys, IncRonald goodstein, first shot Logic simulation andSteven Sharp Cadence Design Systems, IncAlec Stanculescu. Fintronic USA IncDesignStuart Sutherland. Sutherland HDL IncMark Hartog, Synopsys incGordon Vreugdenhil, Mentor Graphics CorporationJames Markevitch, Evergreen Technology GroupJason Woolf, Cadence design Systems, IncCopyright C 2006 IEEE. All rights reservedThe behavioral Task Force had the following membership:Steven Sharp, Cadence Design Systems, InC, ChairKurt Baty, WFSDB ConsultingJay lawrence. Cadence design Systems. IncStefen Boyd, Boyd TechnologyFrancoise Martinolle, Cadence Design Systems, IncShalom Bresticker, Intel CorporationKathryn McKinley, Cadence Design Systems, IncDennis brophy, Mentor graphics corporationMichael mcnamara. Verisity LtdCliff Cummings, Sunburst Design, IncDon Mills, LCDM EngineeringSteven Dovich, Cadence Design Systems, IncMehdi Mohtashemi, Synopsys, IncTom Fitzpatrick, Mentor Graphics CorporationKaren Pieper, Synopsys, IncRonald Goodstein, First Shot Logic Simulation andBrad Pierce, Synopsys, IncDesignDave Rich, Mentor Graphics CorporationKeith Gover, Mentor Graphics CorporationSteven Sharp, Cadence Design Systems, IncMark Hartoog, Synopsys, IncAlec Stanculescu. Fintronic USAEnnis Hawk, Jeda TechnologiesStuart Sutherland. Sutherland hdl. IncAtsushi kasuya, Jcda TechnologicsGordon Vrcugdcnhil, Mentor Graphics CorporationThe PLI Task Force had the following membershipCharles Dawson, Cadence Design Systems, Inc, ChairGhassan Khoory, Synopsys, Inc Co-chairTapati Basu, Synopsys, IncMichael rohleder. Freescale Semiconductor. IncSteven Dovich, Cadence Design Systems, IncRob Slater, Freescale Semiconductor IncRalph duncan, Mentor Graphics CorporationJohn Stickley, Mentor Graphics CorporationJim garnett, Mentor Graphics CorporationStuart Sutherland. Sutherland HDL. incJoao geada CLK Design AutomationBassam Tabbara. Novas software. IncAndrzej litwiniuk, Synopsys, IncJim Vellenga, Cadence Design Systems, IncFrancoise Martinolle, Cadence Design Systems, IncDoug Warmke, Mentor Graphics CorporationSachchidananda Patel, Synopsys, IncIn addition, the working group wishes to recognize the substantial efforts of past contributorsMichael McNamara, Cadence Design Systems, Inc1364 Working Group past chair(through September 2004)Alec Stanculescu, Fintronic USA, 1304 Working Group past vice-chair(through June 2004)Stefen Boyd, Boyd Technology, ETF past co-chair(through November 2004)The following members of the entity balloting commitlee voted on this standard. Balloters may have votedfor approval, disapproval, or abstentionAccelleraIntel CorporationBluespec, Inc.Mentor Graphics CorporationCadence Dcsign Systcms, IncSun microsystems, IncIntronic u.s.aSunburst design, IncIBMSutherland hdl lncInfineon TechnologiesSynopsys, IncCopyright C 2006 IEEE. All rights reservedWhen the IEEE-SA Standards Board approved this standard on 8 November 2005, it had the followingmembershipSteve M. mills. chairRichard h. hulett vice chairDon wright Past chairJudith gorman. secretaryMark d. bowmanWilliam B HopfT W. olsenDennis B. BrophyLowell G. JohnsonGlenn parsonsJoseph brudeHerman KochRonald c. petersenRichard coxJoseph L. Koepfinger*Gary s. RobinsonBob davisDavid J lawFrank stoneJulian forster kDaleep c mohlaMalcolm v thadenJoanna n. gueninPaul nikolichRichard l. townsendS. HalpJoe d. watseRaymond hapemanHoward L, wolfmanAlso included are the following nonvoting Ieee-Sa Standards board liaisonsSatish K. aval, NRC RepresentativeRichard Deblasio, DOE RepresentativeAlan H. Cookson, NIST RepresentativeMichelle d, trIEEE Standards Project EditoCopyright C 2006 IEEE. All rights reservedContentsOverview1. 2 Conventions used in this standard1.3SIption1 4 Use of color in this standard1.5 Contents of this standard1.6 Deprecated clauses……….….….….…1.7 Header file listings....18 Examples…………………1.9PNormative references63. Lexical conventions83.1 Lexical tokens3.2 White space3. 3 Comments中··…·········:···············中·····“:·:·:·4·····“··········3. 4 Operators3. 5 Numberssteger constants3.5.2 Real constants123.5.3 Conversion123.6 Strings123.6. 1 String variable declaration133.6.2 String manipulation133.6.3 Special cha3.7 Identifiers. keds, and syste143.7.1 Escaped identifiers143.7.2 Keywords153.7.3 System tasks and functions3.7.4 Compiler directives153.8 Attrib163.8.1 Examples3.8.2 SyIata typ··4.1 Val214.2 Nets and variables4.2.1 Net declarations4.2.2 Variable declarations4.3V4.3.1g v244.3.2 Veclor net accessibility44.4 Strengths4.4.1 Charge strength4.4.2 Drive strength.....卓········中····“·········:·····················:········254.5 Implicit declarations4.6 Net types………264.6.1 Wire and tri nets264.6.2 Wired nets4.6.3TCopyright C 2006 IEEE. All rights reserved4.6.4 Trio and tri l nets4.6.5 Unresolved nets4.6.6 Supply nets324.7 Regs324.8 Integers, reals, times, and realtime4.8.1 Operators and real numbers4.8.2 Conversion4.9 Arrays4.9.1Net arrays…·中·····:··344.9.2 reg and variable arrays344.9.3 Memories4.10 Parameters…………………354.10.1 Module parameters…364.10.2 Local parameters(localparam““374.10.3 Specify parameters……384. Name spaces…39Expressions……5.1 Operators41Operators with real operands425.1.2 Operator precedence………5.1.3 Using integer numbers in expressions…….445.1.4 Expression evaluation order……2451. 5 Arithmetic operators5.1.6 Arithmetic expressions with regs and integers5. 1.7 Relational operators485.1.8Equ495.1.9 Logical operators…495.1.10 bitw isators505.1.11 Reduction operators5.112 Shift operators…….535. 1. 13 Conditional operator535.1. 14 Concatenations545.2 Operands………5.2. 1 Vector bit-Select and part-select addressing..565.2.2 Array and memory addressing.......,.……5.2.3ings585.3 Minimum, typical, and maximum delay expressions5.4 Expression bit lengths5.4.1 Rules for expression bit lengths65.4.2 Examole of expression bit-length problerpl635.4.3 Example of self-determined expressions.645.5 Signed expressions5.5.1 Rules for expression types.....5.5.2 Steps for evaluating5.5.3 Steps for evaluating an assignment5.54 Handling X and Z in signed expressions………5.6 Assignments and truncation6. Assignments……………686.1 Continuous assignments686. 1. 1 The net declaration assignment6.1.2 The continuous assignment statement·····中···:·:·4·中·····6.1.371Copyright C 2006 IEEE. All rights reserved
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