microTCA规范
PICMG microTCA.0 Specification RC1.0ContentsIntroduction and objectives1.1 Overview1.2 Introduction1.2.1S1.2.2 MicroTCa implementation options1画1-21.2.3 Design goals1-21.2.4 Elements of microtca1-312.5 Theory of operation……着1国面1面日正1-81.3 Micro TCA enclosure types191.3.1 Single Shelf implementation191.3.2 TWo Tier mⅸ ed Width Shelf implementation.…….….….….….….….…....1-101.3.3 Two-Tier fixed Single Width Shelf implementation ....................1-101.3.4 Back-to-Back Shelf implementation.1-101.3.5 Cube Shelf implementation..1-101.3.6 Pico Shelf implementations1111.3.7 Other implementation options1111.4 Application examples1-1114.1 Base station…1-111.42 Router1-121.4.3∨ olP node.….1-121.4.4 Other Telecom Network applicationsE画1-121.4.5 Enterprise applications1-131.4.6 Other applications.....1-131.4.7 Consumer applications1-131.5 Special word usage1-131.6 Conformance1-141.7 Dimensions1-141.8 Regulatory guidelines1-141.9 Reference specifications1.10 MicroTCA0 Specification contributor……1-151-161.11 Name and logo usage1-161.12 Intellectual property……1-171.12.1 Necessary claims1,,面,国国,,国面正∴1-181.12.2 Unnecessary claims11181.12. 3 Third party disclosures1-181.13 Glossary1-192Mechanical2-12.1 Mechanical overview∴………….2-12.1.1 Terminology…2-22.1.2 Typical arrangement examples2-22.2 Dimensions, tolerances, drawing symbols, and nomenclature2-62.3 Mechanical concept2-82.4 AdvancedMC Module orientation, location, and positioning2-1624.1 Module orientation.2-162.4.2 Module positioning, horizontal--mandatory2-172.4.3 Module positioning, vertical-mandatoryU.882-192. 4. 4 Module positioning, depth--mandatory,.42-21PICMG( Micro TCAO Specification Draft RC1. 0, May 26, 2006Do not specify or claim compliance with this Draft Specification2.5 Slot detail dimensions2-222.5.1S|ot..2-222.5.2 Slot configurations, subdividing Slots2-222.5.3 Card guide, Strut, and Card Guide Support Plate(CGSP)…………2232.5.4 Optional Subrack attachment plane2-322.5.5 AdvancedMC Module--optional locking………………………2-342.6 Backplane2-3627 Subrack dimensions2-412.7.1 Mandatory Subrack2-422.8 Shelf2-472.8. 1 Shelf types.2-482.8.2 Shelf width and height…...…2-492.8.3 Shelf depth2-492.8.4 Air filter provision2-502.8.5 ESD wrist strap interface2-502.8.6 Shelf alarm LEDs2-512.9 Cable management2-522. 10 Power entry /Power Module2-562.10.1 Power Module pcb dimensions2-582.10.2 Power Module component height1·面2-632.10.3 Power module face plate2-642.10. 4 Power Module handle/Latch mechanism.2672.10.5 Power module lEDs2-672. 10.6 Power Module EMc gasketing2-672.10.7 Power Module satety covers2-672.10 8 Power module labels2-682.10. 9 Power Module Backplane Connector2-682.11 MCH Module2-692.11.1 Module types2-692.11.2 MCH PCB dimensions.2-702.11.3 MCH Subrack slot details2-772.11. 4 Plug Connector.2-792.11.5 Sequencing and contact area2-812.11.6 MCH positioning2-812. 12 Air flow management面2-822.13 Auxiliary Connector(Zone 2 and zone 3)keying2-832.13.1 Component keep- in height2-842.13.2 Connector keep-in height2-842.133 Keying block…2-852.13.5 AMC0 electrically compatible keying block2.13. 4 Keying block with electrical connections2-86.2-872.14 MicroTCa cube2892.15 MicroTCA Pico2.16 Microtca filler pane的∵面1面面,面2-902-902.17 Cooling Units(CUs)2-912.18 Subrack/Shelf/Cube/Pico performance.2922. 18.1 Load carrying2-922.18.2 Insertion cycles2922.18.3ESD2-922.18.4EMC2-93PICMG MicroTCA. 0 Specification Draft RC1.O, May 26, 2006Do not specify or claim compliance with this Draft Specification2. 18.5 Safety2-932.18.6 Physical Slot and Tier numbering2932.19 Subrack/Shelf environmental2-962.19. 1 Subrack shock and vibration2-962.19.2 Earthquake.........2-962.19.3 Flammability2-962.19.4 Atmospheric2-962. 19.5 Thermal2-972.19.6 Acoustic∴…………………2972.19.7 Surface temperatures2-972.20 References2-973 Hardware platform management3-13.1 Overview3.1.1 Micro Tca Carrier model3-13.1.3 Relationship with IPMI, AdvancedMC, and AdvancedTCA.3.1.2 MicroTCA management architecture3-23-73.1.4 Key differences from PICMG 3.0 and AMC.0 specifications..........3-73.1.5 PICMG properties and FRU Device ID assignments3-93.2 Management-related interconnects3-113.2.1 AdvancedMc interconnects3-113.2.2 Power Module and Cooling Unit interconnects3.2.3 Guidelines for OEM Module interconnects and management3-133-143.2.4 Carrier FRU Information device requirements.3-153.25 Microtca carrier interconnects3-193.3 Carrier Manager.…….…..…...…3-203.3.1 MCH Face Plate indicators3-223.3.2 Payload Interface3-223.3.3 Carrier Manager IP address3-223.3.4 IPM event support∴3-243.3.5 Redundant MCH operation3-253.3.6 Addressing3-263.3.7 Carrier number3-293.3.8 Location information34 Shelf Manager…3-383. 4.1 Shelf Manager configuration options383.4.2 Differences from the AdvancedTca shelf Manager3-403.4.3 Shelf-Carrier Manager Interface翻套国画1面,国面,1面D国画面国3-423.4.4 Shelf Manager IP addre3-433.5 MCMC requirements3453.6 EMMC requirements3-463.7 Operational state management3-483.7.1 Carrier Manager start up……….….….….………..……3483.7.2 Shelf Manager actions on Carrier detection3-483.7.3 Normal Shelf operation1B面面国B3-483.7.4 Abnormal situation handling3-4938 Power management.……3-493.8.1 Power clapping国面3-503.8.2 Micro T CA Carrier Power Management records.3-513.8.3 Early power management356PICMG( Micro TCAO Specification Draft RC1. 0, May 26, 2006Do not specify or claim compliance with this Draft Specification3.8.4 Normal power management.3-573.8.5 Power management commands and sensors3-593.8.6 Abnormal power condition handling3-673.9 Cooling management3-693.9.1 Fan geography.…3-703.9.2 Cooling control…3-713.9.3 Normal cooling operation3-723.9.4 Abnormal cooling operation3-733.9.5 Fan tachometer sensors3-733.9.6 Temperature sensors翻画1国翻B1B…3-733.10 Electronic Keying3-743.10.1 Micro TCA Carrier point-to-point connectivity information3-753.10.2 Module point-to-point connectivity information.3-773.10.3 AMC Port state commands3-783.10.4 Clock b- Keying……3-783.11 Telco alarm management3-73. 12 System Event log…………3-863.13 Sensor management3-863.13.1 Guidelines and requirements for fru sensor events3-863.13.2 MCMC SDR requirements.3-873.13.3 EMMC SDR requirements3-883.13.4 Carrier Manager SDR requirements3-883.14 fru Information.3-913. 14.1 EMMC FRU Information3-913. 14.2 MCMC FRU Information3-913.143 Carrier FRu Information3-923. 14.4 Shelf fru information面国面国面3-923.15 PMI message bridging……….3-933.15.1 Message bridging process3-933.16 PMI functions and command3-943. 16.1 Required IPMI functions..3-953.16.2 Command assignments3-973.17 FRU records, sensors and entity Ids∴3-1084 Power…4-14.1 Overview4-14.2 Loads on the Power Subsystem4-24.2.1 Microtca carrier hub(MCH),………,………………………24-24.2.2 Cooling Units4-74.2.3 Advanced mezzanine cards4-104.3 Power architecture4-134.3.1 Basic functionality4-134.3.2 Partitioning of the Power Subsystem:.::a:.4-154.3.3 Power sources4-154.3. 4 Power Subsystem redundancy4-164.3.5 System Grounding considerations4-214.3.6 Power distribution and backplane considerations4-234.4 Control and monitoring of the Power Subsystem4-2444.1 PM-EMMCs4-244.4.2 Geographic Address4-24PICMG MicroTCA. 0 Specification Draft RC1.O, May 26, 2006Do not specify or claim compliance with this Draft Specification4.4.3|PMB-04-2444.4Ps1[S|o#4-254.4.5EN[Slof]#,…4-2544.6 PWRON_[Sot]…4-254.4.7PSPM#4-2644.8 PM-EMMC watchdog timer……4264.4.9 Power Module oK4-2744.10 Power module reset4-274.4.11 System power-up4-274.4.12 Input voltage sensors1国面面量面1国面4-294.4.13 Temperature sensors4-294414 Power module extraction switch4-304,415 Blue lED4-304.4.16LED14-314 4.17 Other leds4-314.5 Connectors4-314.5. 1 Power Module Output Connector4-324.5.2 Power Module Input Connectors81国面面4-324.6 Single-Width,Fu‖- Height Power Module…∴4-334.6.1 Inputs4-344.6.2 Outputs4-354.6.3 Bulk supply current limit4-384.6.4 Control and monitoring………………………4-384.6.5 Redundancy4-384.6.6 Mechanical4-4546.7 Thermals.8...8.88.84-45画·面4.6.8 Regulatory.4-4547 Other mechanical considerations…4-464.7.1 Double-Width form factor4-464.7.2 Form factors other than Full-Height4-464.8 Power source considerations.4-464.8.1 DC power feeds4-474.8.2 AC power feeds4-554.9 References4-605 Thermal5.1 Overview5-15.2 AMC. 0 Modules and microtCa国着画5-15.3 AMC.0 Carriers and microtca5.4 Subrack slot5-25.5 Airflow path5.6 AMC.0 Modules and power dissipation.5-35-35.7 MicroTCA system cooling configuration……….….….…....545. 8 Air distribution in a slot5-45.9 Air inlet and exhaust5-55. 10 Slot cooling capability5-55. 11 Module cooling requirements●5.12 Standard air.5-75.12.1 Derivatie5.122 Barometric changes due to weather....…...……….57PICMG( Micro TCAO Specification Draft RC1. 0, May 26, 2006Do not specify or claim compliance with this Draft Specification5.13 Slot impedance curve.5-85.14 Slot fan flow curve5.15 Cooling Unit failure5-85.16 Filters5.17 System sensors….…….….……5-95.18 Thermal and operating environment5-105.19 Thermal and cabling5-105.20 Simulation and impedance testing5-105.20.1 AdvancedMC/MCH reference Module..5-115.20.2 Power Unit reference module∴5-125.21 Simulation environment5.22 Thermal dynamic modeling5-135.23 Fluid networking modeling5.24 Acoustic noise5-135.25 Surface temperature5-145.26 Design recommendations5-155.27 Cooling limitations and examples..5-175.28 References1面5-226 Interconnect6-16.1 Introduction.…6-16.2 Fabric interface6.2.1 Backplane fabric interface support requirements6-26.2.2 MCH fabric interface support requirements6.3 MCH Specific Interfaces6-46.3.1 MCH update Channel interface6-46.3.2 MCH cross-over Channel interface.6-56. 3. 3 MCH PWR ON interface6-66.3.4 Inter-MCH IPMB-L interface6.4 Synchronization clock interface6.4.1 Signal descriptions6-86. 4.2 Clock architectures6-96.4.3 Non-Telecom and Telecom clocks6-136.5 JTAG interface.…6-136.5.1 JSM Overview6-146.5.2 JSM Signaling Overview6-166.5.3 JSM Interface to mch16.54 JSM Interface to mch2.……6-186.5.5 JSM Interface to Advancedmcs.6-196.5.6 JSM Interface to Power modules.6-226.5.7 JSM Master mode selection6-236.5.8 JSM Interface to External tester..6-246.5.9 MCH JTAG6-266.5. 10 Power module jtAG6-276.6 MicroTCA Interface topologies1画6-276.6. 1 Topology models6-286.6.2 Correlation to AdvancedMc fabric regions6-296.7 MCH Connector pin allocation6-306.7.1 Pin naming conventions6-316.7.2 Fabric interface naming conventions6-31PICMG MicroTCA. 0 Specification Draft RC1.o, May 26, 2006Do not specify or claim compliance with this Draft Specification6.7.3 Synchronization clock interface naming convention6-316.7.4 MCH Connector pin list……………6-326.8 System examples.6-386.8. 1 Redundant MicroTCA system6-386.8.2 Variant redundant microtca interconnect6-416.8.3 Non-redundant MicroTCA system6-45Connectors7-17.1 General information7-17.2 AdvancedMC Backplane Connectors7-17.2.1 AdvancedMC Backplane Connector pin list7-27.2.2 AdvancedMC Backplane Connector dimensions7-27.2.3 Advancedmc backplane connector pcb layout∴7-67. 2. 4 AdvancedMC Backplane Connector electrical characteristics7-107.2.5 AdvancedMC Backplane Connector high-speed characteristics7-147.2.6 AdvancedMC Backplane Connector mechanical characteristics7-187.3 Micro TCa Carrier hub connectors7-197.3.1 Micro TCA Carrier Hub Connector pin list7-197.3.2 Micro TCA Carrier Hub mating interface design7-207.3.3 Micro TCA Carrier Hub backplane connector7-227.3. 4 Micro TCA Carrier Hub Connector Backplane PCB layout7-237. 3.5 Micro tca Carrier Hub connector electrical characteristics7-247.3.6 Micro TCA Carrier Hub Connector high-speed characteristics7-2573.7 Micro tCa Carrier hub connector mechanical characteristics7-297.4 Power Module Output Connector7.4.1 Power Module Output Connector pin list and mating sequence7-317.4.2 Power Module Output Connector dimensions7-327. 4.3 Power Module Output Connector Backplane PCb layout7-347.4.4 Electrical characteristics for power Module output connector.7-367.4.5 Power Module Output Connector mechanical characteristics7-397.5 Power Module Input Connector7.5.1 Power Module Input Connector pin list and mating sequence7-417.5.2 Power Module Input Connector dimensions7-427.5.3 Electrical characteristics for Power Module Input Connector7-477.5.4 Power Module Input Connector mechanical characteristics7-517.6 AdvancedMC Auxiliary Connector7-537.7 Test schedule7-547.7.1 Specimen measurement arrangements7-547.7.2 Test schedule tables.7-647. 8 References.7-798 Regulatory requirements and industry standard guidelines8-18.1 Regulatory……8-18.1.1 Safety8-18.1.2 Electromagnetic compatibility..……………8-28.1.3 Ecology standards.8-28.2 Telecommunications industry standards requirements8-38. 2. 1 EMC/safety requirements for the telecommunications industry.......8-38.2.2 Environmental requirements for the telecommunications industry ..............8-48.3 Reliability/MTBF standards8-7PICMG( Micro TCAO Specification Draft RC1. 0, May 26, 2006Do not specify or claim compliance with this Draft Specification8.4 Cross reference list8.5 FRU test guidelines∴8-78.5. 1 FRU safety test8-88.5.2 FRU EMC testing.8-88.5.3 FRU environmental testing8-9a Module mis-insertion considerationsA-1A 1 MCH Module mis-insertion combinationsA-2A 2 AdvancedMc module mis-insertion combinationsA-5A3 Power management implicationsA-8A 4 System management implicationsA-8A.4.1 Optional MMC instance on MCH ModuleA-9A.4.2 Using an AdvancedMC in an MCH SlotA-13A.4.3 Using an mch in an AdvancedMc SlotA-15A.4.4 Detecting mis-insertionsA-16A.5 Hardware implicationsA-1A. 5. 1 GNd pins at same locations........A-20A.5.2 PSO# and PS1# pins at same locationsA-23A.5.3 PWR and MP pins at same locationsA27A.5. 4 PWR ON pinA-29A.5.5 Ga[2: 0] pins at same locations道1面4…A-31A.5.6 ENABLE# pin at same locationA-35A.5.7 SDA L and SCL L pinsA-37A 5.8 JTAG pinsA-38A 5.9 Cross-over pinsA-39A.5. 10 TMREQ#, 12C SDA, and I2C SCL pins…A-39B Requirement list….B-1PICMG MicroTCA. 0 Specification Draft RC1.O, May 26, 2006Do not specify or claim compliance with this Draft Specification
- 2020-06-05下载
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altera公司IP核使用手册.PDF
altera公司IP核使用手册,对于学习EDA技术的学生或工程师有用A吉RAContentsChapter 1. About this MegaCore FunctionRelease informat1-1Device Family Support···Introduction.··········FeaturesOpen core plus evaluation1-3Performance···Chapter 2. Getting StartedDesign Flow衡·鲁·,看·,音番2-1Megacore Function walkthrough2-2Create a New quartus II Pi2-2Launch the mega Wizard Plug-in ManagerStep 1: Parameterize2-5Step 2: Set Up SimulationStep 3: Generate..,2-11Simulate the design2-13Compile the design2-13Pa Device2-14Set Up Licensing2-15ppend the license to yourdat file2-15Specify the License File in the Quartus II Software...2-15Example Simulation and Compilation..2-16Example quartus Ii project2-16Example simulation with Test Vectors,,,,,,2-16Chapter 3. SpecificationsyperTransport Technology Overview1HT SyStems3-2HT Flow ControlHyper Transport MegaCore Function SpecificationPhysical InterfaceSynchronization and alignment ...Protocol interfClocking Options.......HyperTransport Mega Core Function Parameters and HT Link Performance3-10Signals3-14CSR Module...3-31OpenCore plus time-Out BehaviorAppendix A. ParametersIntroduction鲁鲁鲁A-1Parameter listsDevice Family and Read Only registers···········,,,,,,,,,,A-1Base Address Registers番鲁,A-2Clocking OptionsA-3Advanced settingso March 2009 Altera corporationHyperTransport MegaCore Function User GuideAppendix B. Stratix Device Pin AssignmentsIntroductionB-1GuidelinesAppendix C. Example designGeneral descriptionAdditional informationRevision historyInto-lHow to Contact alteraInfo-1Typographic Conventions ..........Info-2Hyper Transport MegaCore Function User Guideo March 2009 Altera CorporationA吉RA1. About this MegaCore FunctionRelease InformationTable 1-1 provides information about this release of the Hyper Transport Mega CoretfunctioTable 1-1. Hyper Transport Mega Core Function Release InformationitenlDescription∨ ersion9.0Release dateMarch 2009Ordering codeIP-HTProduct ID(s)0098Vendor iD(s)6AF7Altera verifies that the current version of the quartus@ll software compiles theprevious version of each MegaCore function. Any exceptions to this verification arereported in the Mega Core lP Library release Notes and Errata. Altera does not verifycompilation with Mega Core function versions older than one releaseDevice Family SupportMegaCore functions provide either full or preliminary support for target Alteradevice families:Full support means the Mega Core function meets all functional and timingrequirements for the device family and may be used in production designsa Preliminary support means the Mega Core function meets all functionalrequirements, but may still be undergoing timing analysis for the device family;itmay be used in production designs with cautionTable 1-2 shows the level of support offered by the Hyper Transport MegaCorefunction for each of the altera device familiesTable 1-2. Device Family SupportDevice FamilySupportHard Copy Stratix@FullStratixFulStratix IIFulStratix‖GXPreliminaryStratix GXOther device familiesNo supportC March 2009 Altera CorporationHyperT ransport Mega Core Function User Guide1-2Chapter 1: About this MegaCore FunctionIntroductionIntroductionThe Hyper Transport Mega Core function implements high-speed packet transfersbetween physical(PhY) and link-layer devices, and is fully compliant with theHyperTransport l/O Link Specification, Revision 1.03. This Mega Core function allowsdesigners to interface to a wide range of Hyper TransportTm technology(hT)enableddevices quickly and easily, including network processors, coprocessors, videochipsets, and ASICsFeaturesThe Hyper Transport Mega Core function has the following features8-bit fully integrated hT end-chain interfacePacket-based protocolDual unidirectional point-to-point linksUp to 16 Gigabits per second(Gbps)throughput(8 Gbps in each direction)200, 300, and 400 MHz DDR links in Stratix and Stratix GX devices200, 300, 400, and 500 MHz ddr links in Stratix II and Stratix II GX devicesLow-swing differential signaling with 100-Q2 differential impedanceHardware verified with Hyper fransport interfaces on multiple industry standardprocessor and bridge devicesFully parameterized mega core function allows flexible, easy configurationFully optimized for the altera stratix Il, Stratix, Stratix GX, and Stratix II GXevice famillesApplication-side interface uses the Altera AtlanticTM interface standardManages Hr flow control, optimizing performance and ease of useIndependent buffering for each HT virtual channelAutomatic handling of ht ordering rulesStalling of one virtual channel does not delay other virtual channels(subject toorderingFlexible parameterized buffer sizes, allowing customization depending onsystem requirementsUser interface has independent interfaces for the HT virtual channels, allowingindependent user logic designCyclic redundancy code(crc) generation and checking to preserve data integrityIntegrated detection and response to common HT error conditions■ CRC errorsEnd-chain errorsFully integrated HT configuration space includes all required configuration spaceregisters and HT capabilities list registersHyper Transport MegaCore Function User Guideo March 2009 Altera CorporationChapter 1: About this MegaCore FunctionPerformance32-bit and 64-bit support across all base address registers bars)automatically handles all csr space accessesVerilog HDL and VHdL simulation supportOpen Core Plus EvaluationWith the Altera free Open Core Plus evaluation feature, you can perform the followingSimulate the behavior of a mcgafunction(Altera MegaCore function or AMPPmegafunction) within your systema Verify the functionality of your design, as well as quickly and easily evaluate itssize and speedGenerate time-limited device programming files for designs that includeMegaCore functionsProgram a device and verify your design in hardwareYou only need to purchase a license for the Mega Core function when you arecompletely satisfied with its functionality and performance and want to take yourdesign to productiono For more information about Open Core Plus hardware evaluation using theHyperTransport MegaCore function, refer to"Open Core Plus Time-Out Behavior"onpage 3-40 and AN 320: Open Core Plus Evaluation of megafunctionsPerformanceThe Hyper Transport Mega Core function uses 20 differential I/O pin pairs and 2single-ended I/O pins, requiring 42 pins total. Table 1-3 through Table 1-5 showtypical performance and adaptive look-up table (alut) or logic element (LE)usagefor the HyperTransport MegaCore function in Stratix II GX, Stratix IL, Stratix, andStratix GX devices respectively, using the Quartus@ II software version 7.1Table 1-3 shows the maximum supported data rates in megabits per second(Mbps)by device family and speed gradeTable 1-3. Maximum Supported Hyper Transport Data Rates (Note 1)Speed GradeDevice Family-36Stratix ll GX devices 1000 Mbps 1000 Mbps 800 MbpsNA(2)N/A(2NA(2)Stratix devices1000 Mbps 1000 Mbps 800 Mbps N/A(2)NA(2)NA(2)Stratix devicesN/A(2N/A(2)00 Mbps 800 Mbps 600 Mbps400 MbpsFlip-Chip packagesStratix devicesNA(2)NA(2)NA(2)600 Mbps400 Mbps400 Mbps(Wire Bond packagesStratix GX devicesN/A(2) N/A(2)800 Mbps 800 Mbps 600 Mbps N/A(2)Notes to table 1-3(1)Rates are per interface bit. Multiply by eight to calculate the uni-directional data rate of an 8-bit inter face(2) Devices ot this speed grade are not ottered in this device familyC March 2009 Altera CorporationHyperTransport Mega Core Function User GuideChapter 1: About this MegaCore FunctionPerformanceTable 1-4 shows performance and device utilization for the Hyper TransportMegaCore function in Stratix II and Stratix II GX devicesTable 1-4. Hyper Transport Mega Core Function Performance in Stratix ll and Stratix ll GX DevicesParametersMemoryUserRXCombinationalHT Link InterfacePosted Non-Posted Response ClockingALUTSLogicfMAX(MHz) MAx(MHz)Buffers BuffersBuffers Option(12)Registers M4K M512 ( 3)3)Shared3.5005200120500125(4RX/TX/Ref35005200500Ref/x8Shared36005400160500>150RX/TXShared4.0006,00016150RX/TX16Shared4,1006,200500125(4)RX/TX/RefShared4.1006200500125(4Ref/TxShared4.2006400160150RX/TXNotes to table 1-4.Refer to " Clocking Options "on page 3-7 for more information about these options(2 )Other parameters(BAR configurations, etc. )vary the alut and Logic Register utilization numbers by approximately +/-200(3)Figures for -3 speed grade devices only(4) When using the Shared Rx/Tx/Ref and Shared Ref/Tx options, the user interface frequency is limited to exactly the ht frequency divided byTable 1-5 shows performance and device utilization for the Hyper TransportMegaCore function in Stratix and Stratix GX devicesTable 1-5. Hyper Transport Mega Core Function Performance in Stratix and Stratix GX DevicesUser Interface fmaxParametersUtilizationHT Link fMAX MHz)MHZ)RXRXSpeed GradePosted Non-Posted Response Clocking Option LEsM4KBuffers BuffersBuffers)(2 Blocks.5-66Shared rx/tx/ref1240010073)100734448888Shared Ref/Tx 7, 60014400400100{3)100(3)Shared rxtx7,90016400400>125>100Shared rxtx8.900125>100168Shared Rx/T×Ref9,400124004001003)100316Shared ref/ ix9.500144001003)10073)16Shared rx/x9.700400125Notes to table 1-5:(1)Refer to Clocking Options"on page 3-7 for more information about these options(2 )Other parameters( BAR configurations etc. )vary the LE utilization by approximately +/-200 LES(3 )When using the Shared Rx/Tx/ Ref and Shared Ref/Tx options, the user interface frequency is limited to exactly the hT frequency divided by fourHyper Transport MegaCore Function User GuideC March 2009 Altera CorporationA吉RA2. Getting StartedDesign FlowTo evaluate the HyperTransport Mega Core function using the Open Core Plus feature,include these steps in your design flowObtain and install the HyperTransport Mega Core functionThe HyperTransport Mega Core function is part of the MegaCore IP Library, which isdistributed with the Quartus ii software and downloadable from the altera websitewww.altera.como For system requirements and installation instructions, refer to Quartus II InstallationLicensing for Windows and Linux Workstations on the Altera website atwww.altera.com/literature/lit-qts.ispFigure 2-1 shows the directory structure after you install the HyperTransportMegaCore function, where is the installation directory. The default installationWindows is C: altera ; on Linux it islopt/alteraFigure 2-1. Directory StructureInstallation directorypContains the Altera MegaCore IP Library and third-party IP coresalteraContains the Altera MegaCore IP LibrarycommonContains shared componentshtContains the Hyper Transport Hyper Transport Megacore function files and documentationdocContains the documentation for the Hyper Transport MegaCore functionlibContains encrypted lower-level design filesexampleContains the design example for the Hyper Transport Mega Core function2. Create a custom variation of the Hyper Transport Mega Core function3. Implement the rest of your design using the design entry method of your choice4. Use the IP functional simulation model to verify the operation of your designo For more information about Ip functional simulation models, refer to the SimulatingAltera IP in Third-Party Simulation Tools chapter in volume 3 of the Quartus II Handbook5. Use the Quartus II software to compile your designC March 2009 Altera CorporationHyperT ransport Mega Core Function User Guide2-2Chapter 2: Getting StartedMega Core Function WalkthroughIg You can also generate an Open Core Plus time-limited programming file,which you can use to verify the operation of your design in hardware6. Purchase a license for the hypertransport Mega Core functionAfter you have purchased a license for the Hyper transport mega Core functionfollow these additional steps1. Set up licensing2. Generate a programming file for the Altera device(s)on your board3. Program the Altera device(s)with the completed designMegaCore Function WalkthroughThis walkthrough explains how to create a custom variation using the AlteraHyper Transport IP Toolbench and the Quartus II software, and simulate the functionusing an ip functional simulation model and the modelsim software when you arefinished generating your custom variation of the function, you can incorporate it intoⅴ our overall projectIe IP Toolbench allows you to select only legal combinations of parameters, and warnsou of any invalid configurationsIn this walkthrough you follow these stepsCreate a New Quartus II Projecta Launch the MegaWizard Plug-in Manager■Step1: Parameterizea Step 2: Set Up Simulation■Step3: Generate■ Simulate the designTo generate a wrapper file and Ip functional simulation model using default values,omit the procedure described in"Step 1: Parameterizeon page 2-5Create a New Quartus ll ProjectCreate a new Quartus II project with the New Project Wizard, which specifies theworking directory for the project, assigns the project name, and designates the nameof the top-level design entityTo create a new project, perform the following steps1. On the Windows Start menu, select Programs> Altera> Quartus II tostart the Quartus lI software. Alternatively, you can use the Quartus II Web editionsoftware2. In the Quartus II window, on the File menu, click New Project Wizard. If you didnot turn it off previously, the New Project Wizard Introduction page appears3. On the New Project Wizard Introduction page, click NextHyper Transport MegaCore Function User Guideo March 2009 Altera Corporation
- 2020-12-05下载
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