SAP PLM 产品生命周期管理

构建工具gradle-4.10.2。From mobile apps to microservices, from small startups to big enterprises, Gradle helps teams build, automate and deliver better software, faster.

小波图像融合matlab实现源代码 ，利用小波实现了图像融合。含图片

特征降维是模式识别中重要的一步，从图像中提取的原始特征往往维度较高，需要对其降维处理。基于AdaBoost的特征降维是具有良好的特征选择能力，其对每一维特征训练若分离器，根据分类效果调整权重，并最终选择具有分类信息的特征组合。

乐优商城门户网站，门户系统面向的是用户，安全性很重要，而且搜索引擎对于单页应用并不友好。因此门户系统不再采用与后台系统类似的SPA（单页应用）。依然是前后端分离，不过前端的页面会使用独立的html，在每个页面中使用vue来做页面渲染。

计算机网络实验报告——一个小型校园网的设计与组建有截图和网络设计图12.1 实验目的 计算机网络是一门实践性较强的技术，课堂教学应该和实践环节紧密结合。计算机网络实验培养学生具有独立进行计算机网络架构和设计能力，提高学生的网络设备使用水平，以及将理论与实践相结合的能力。 12.2 实验环境及设备 2台路由器、2台交换机、3台PC机 12.3 实验的内容和要求 根据要求，设计并搭建一个校园网。要求进行子网划分和结构设计，并将网络结构建立起来。最后完成网络设备的调试。 12.4 实验说明

变尺度法的dfp算法，包括确定搜索区间和步长，适合二元二次的目标函数

里面实现了最新的一个国外文章里的memristor模型，还编写了用户接口和GUI，很实用，很好的学习资料。

Verilog的IEEE标准，比较新的一个吧应该是IEEE Std 1364 TM-2005(Revision of IEEE Std 1364-2001)lEE Standard for VerilogHardware Description LanguageSponsorDesign Automation Standards Committeeof theIEEE Computer SocietyAbstract: The Verilog hardware description language(HDL) is defined in this standard. VerilogHDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine-readable and human-readable, it supports the development, verificationsynthesis, and testing of hardware designs; the communication of hardware design data; and themaintenance, modification, and procurement of hardware. The primary audiences for this standardare the implementors of tools supporting the language and advanced users of the languageKeywords: computer, computer languages, digital systems, electronic systems, hardware, hardware description languages, hardware design, HDL, PLI, programming language interface, Verilog,Verilog HDL, verilog PllThe Institute of Electrical and Electronics Engineers, Inc3 Park Avenue. New york. NY 10016-5997 USACopyright@ 2006 by the Institute of Electrical and Electronics Engineers, IncAll rights reserved Published 7 April 2006. Printed in the United states of AmericaIEEE is a registered trademark in the U.S. Patent Trademark Office, owned by the Institute of Electrical and ElectronicsEngineers, IncorporatedVerilog is a registered trademark of Cadence Design Systems, IncPrint:|sBN0-738148504SH95395PDFSBN0-7381-48512SS95395No part of this publication may be reproduced in any form, in an electronic retrieval system or otherwise, without the priorwritten permission of the publisher.IEEE Standards documents are developed within the IEee Societies and the Standards CoordinatingCommittees of the iEEE Standards Association (IEEE-SA)Standards board The ieee develops its standardsthrough a consensus development process, approved by the american National Standards Institute, which bringstogether volunteers representing varied viewpoints and interests to achieve the final product. Volunteers are notnecessarily members of the Institute and serve without compensation. While the ieee administers the processand establishes rules to promote fairness in the consensus development process, the ieee does not independentlyevaluate, test, or verify the accuracy of any of the information contained in its standards.Use of an IEEE Standard is wholly voluntary. The ieee disclaims liability for any personal injury, property orother damage of any nature whatsoever, whether special, indirect, consequential, or compensatory, directly orindirectly resulting from the publication, use of, or reliance upon this, or any other iEEE Standard documentThe ieee does not warrant or represent the accuracy or content of the material contained herein, and expresslydisclaims any express or implied warranTy, including any implied warranty of merchantability or fitness for a specific purpose, or that the use of the material contained herein is free from patent infringement. IEEE Standardsdocuments are supplied "AS IsThe existence of an IEEE Standard does not imply that there are no other ways to produce, test, measurepurchase, market, or provide other goods and services related to the scope of the IEEE Standard. Furthermore, theviewpoint expressed at the time a standard is approved and issued is subject to change brought about throughdevelopments in the state of the art and comments received from users of the standard Every IeeE Standard issubjected to review at least every five years for revision or reaffirmation. When a document is more than fiveyears old and has not been reaffirmed, it is reasonable to conclude Chat ils contents, although still of some valuedo not wholly reflect the present state of the art. Users are cautioned to check to determine that they have thelatest edition of any IEEE StandardIn publishing and making this document available, the IEeE is not suggesting or rendering professional or otherervices for, or on behalf of, any person or entity. Nor is the Ieee undertaking to perform any dutyother person or entity to another. Any person utilizing this, and any other ieee Standards document, should relupon the advice of a competent professional in determining the exercise of reasonable care in any givencircumstancesInterpretations: Occasionally questions may arise regarding the meaning of portions of standards as they relate tospecific applications. When the need for interpretations is brought to the attention of IEEe, the Institute will initiateaction to prepare appropriate responses. Since ifff Standards represent a consensus of concerned interests, it isimportant to ensure that any interpretation has also received the concurrence of a balance of interests. For thisreason, IEEE and the members of its societies and standards coordinating committees are not able to provide aninstant response to interpretation requests except in those cases where the matter has previously received formalconsideration. At lectures, symposia, seminars, or educational courses, an individual presenting information onIEee standards shall make it clear that his or her views should be considered the personal views of that individuarather than the formal position, explanation, or interpretation of the IeeeComments for revision of IEEE Standards are welcome from any interested party, regardless of membership aftil-iation with IEEE. Suggestions for changes in documents should be in the form of a proposed change of texttogether with appropriate supporting comments Comments on standards and requests for interpretations shouldaddressed toIEEE-SA Standards Board445 Hoes lanePiscataway, NJ 08854USANoTE-Attention is called to the possibility that implementation of this standard may require use of subjectmatter covered by patent rights. By publication of this standard, no position is taken with respect to theexistence or validity of any patent rights in connection therewith. The IEf shall not be responsible foridentifying patents for which a license may be required by an ieee standard or for conducting inquiries into thelegal validity or scope of those patents that are brought to its attentionAuthorization to photocopy portions of any individual standard for internal or personal use is granted by the Institute of Electrical and Electronics Engineers, Inc, provided that the appropriate fee is paid to Copyright ClearanceCenter. To arrange for payment of licensing fee, please contact Copyright Clearance Center, Customer Service222 Rosewood Drive, Danvers, MA01923 USA; +19787508400. Permission to photocopy portions of any indi-idual standard for educational classroom use can also be obtained through the Copyright Clearance CenterIntroductionThis introduction is not a part of IEEE Std 1364-2005, IEEE Standard for Verilog Hardware Description LanguageThe Verilog hardware description language(HDL) became an IEEE standard in 1995 as IEEE Std 13641995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in a standardtextual format for a variety of design tools, including verification simulation, timing analysis, test analysisand synthesis. It is because of these rich features that verilog has been accepted to be the language of choiceby an overwhelming number of integrated circuit(IC)designersVerilog contains a rich set of built-in primitives, including logic gates, user-definable primitives, switches,and wired logic. It also has device pin-to-pin delays and timing checks. The mixing of abstract levels isessentially provided by the semantics of two data types: nets and variables. Continuous assignments, inwhich expressions of both variables and nets can continuously drive values onto nets, provide the basicstructural construct. Procedural assignments, in which the results of calculations involving variable and netvalues can be stored into variables, provide the basic behavioral construct. a design consists of a set of modules, each of which has an input/output(1/O)interface, and a description of its function, which can be structural, behavioral, or a mix. These modules are formed into a hierarchy and are interconnected with netsThe Verilog language is extensible via the programming language interface(PLI)and the verilog procedural interface(VPi) routines. The Pli/vPi is a collection of routines that allows foreign functions to accessinformation contained in a Verilog hdl description of the design and facilitates dynamic interaction withsimulation. Applications of PLI/VPI include connecting to a Verilog HDL simulator with other simulationand computer-assisted design(CAD)systems, customized debugging TaskS, delay calculators, andannotatorsThe language that influenced Verilog HDL the most was HILO-2, which was developed at Brunel University in England under a contract to produce a test generation system for the British Ministry of DefensehiLO-2 successfully combined the gate and register transfer levels of abstraction and supported verificationsimulation, timing analysis, fault simulation, and test generationIn 1990, Cadence Design Systems placed the Verilog HDL into the public domain and the independentOpen Verilog International(oVi)was formed to manage and promote Verilog HDL. In 1992, the Board ofDirectors of ovi began an effort to establish Verilog hdl as an ieeE standard. In 1993, the first IEeEworking group was formed; and after 18 months of focused efforts, Verilog became an IEEE standard asIEEE Std 1364-1995After the standardization process was complete, the IEEe P1364 Working Group started looking for feedback from IEEE 1364 users worldwide so the standard could be enhanced and modified accordingly. Thisled to a five-year effort to get a much better Verilog standard in IEEE Std 1364-2001With the completion of IEEE Std 1364-2001, work continued in the larger Verilog community to identifyoutstanding issues with the language as well as ideas for possible enhancements. As Accellera began work-ing on standardizing System Verilog in 2001, additional issues were identified that could possibly have led toincompatibilities between Verilog 1364 and System Verilog. The IEEE P1364 Working group was established as a subcomittee of the System Verilog P1800 Working Group to help ensure consistent resolution ofsuch issues. The result of this collaborative work is this standard ieee Std 1364-2005Copyright C 2006 IEEE. All rights reservedNotice to usersErrataErrata,ifanyforthisandallotherstandardscanbeaccessedatthefollowingurL:http:/stan-dards.ieee.org/reading/ieee/updates/errata/index.html. Users are encouraged to check this URL for errataperiodicaInterpretationsCurrentinterpretationscanbeaccessedatthefollowingUrl:http:/standards.ieeeorg/reading/ieee/interp/Index. htmlPatentsAttention is called to the possibility that implementation of this standard may require use of subject mattercovered by patent rights. By publication of this standard, no position is taken with respect to the existence orvalidity of any patent rights in connection therewith. The IEee shall not be responsible for identifyingpatents or patent applications for which a license may be required to implement an IEEE standard or forconducting inquiries into the legal validity or scope of those patents that are brought to its attentionParticipantsAt the time this standard was completed, the ieee P1364 Working group had the following membershipJohny Srouji, IBM, IEEE SyStem verilog Working Group chairTom Fitzpatrick, Mentor Graphics Corporation, ChairNeil Korpusik, Sun Microsystems, Inc, Co-chairStuart sutherland sutherland hdl inc. editorShalom Bresticker, Intel Corporation, Editor through February 2005The Errata Task Force had the following membershipKaren pynopsys,rKurt baty. WFSDB ConsultinDennis marsa. XilinxStefen Boyd, Boyd TechnologyFrancoise Martinolle, Cadence Design Systems, IncShalom Bresticker, Intel CorporationMike McNamara, Verisity, LtdDennis Brophy, Mentor Graphics CorporationDon Mills, LCDM EngineeringCliff Cummings, Sunburst Design, IncAnders nordstrom, Cadence Design Systems, IncCharles dawson, Cadence Design Systems, IncKaren Pieper, Synopsys, IncTom Fitzpatrick, Mentor Graphics CorpoBrad Pierce, Synopsys, IncRonald goodstein, first shot Logic simulation andSteven Sharp Cadence Design Systems, IncAlec Stanculescu. Fintronic USA IncDesignStuart Sutherland. Sutherland HDL IncMark Hartog, Synopsys incGordon Vreugdenhil, Mentor Graphics CorporationJames Markevitch, Evergreen Technology GroupJason Woolf, Cadence design Systems, IncCopyright C 2006 IEEE. All rights reservedThe behavioral Task Force had the following membership:Steven Sharp, Cadence Design Systems, InC, ChairKurt Baty, WFSDB ConsultingJay lawrence. Cadence design Systems. IncStefen Boyd, Boyd TechnologyFrancoise Martinolle, Cadence Design Systems, IncShalom Bresticker, Intel CorporationKathryn McKinley, Cadence Design Systems, IncDennis brophy, Mentor graphics corporationMichael mcnamara. Verisity LtdCliff Cummings, Sunburst Design, IncDon Mills, LCDM EngineeringSteven Dovich, Cadence Design Systems, IncMehdi Mohtashemi, Synopsys, IncTom Fitzpatrick, Mentor Graphics CorporationKaren Pieper, Synopsys, IncRonald Goodstein, First Shot Logic Simulation andBrad Pierce, Synopsys, IncDesignDave Rich, Mentor Graphics CorporationKeith Gover, Mentor Graphics CorporationSteven Sharp, Cadence Design Systems, IncMark Hartoog, Synopsys, IncAlec Stanculescu. Fintronic USAEnnis Hawk, Jeda TechnologiesStuart Sutherland. Sutherland hdl. IncAtsushi kasuya, Jcda TechnologicsGordon Vrcugdcnhil, Mentor Graphics CorporationThe PLI Task Force had the following membershipCharles Dawson, Cadence Design Systems, Inc, ChairGhassan Khoory, Synopsys, Inc Co-chairTapati Basu, Synopsys, IncMichael rohleder. Freescale Semiconductor. IncSteven Dovich, Cadence Design Systems, IncRob Slater, Freescale Semiconductor IncRalph duncan, Mentor Graphics CorporationJohn Stickley, Mentor Graphics CorporationJim garnett, Mentor Graphics CorporationStuart Sutherland. Sutherland HDL. incJoao geada CLK Design AutomationBassam Tabbara. Novas software. IncAndrzej litwiniuk, Synopsys, IncJim Vellenga, Cadence Design Systems, IncFrancoise Martinolle, Cadence Design Systems, IncDoug Warmke, Mentor Graphics CorporationSachchidananda Patel, Synopsys, IncIn addition, the working group wishes to recognize the substantial efforts of past contributorsMichael McNamara, Cadence Design Systems, Inc1364 Working Group past chair(through September 2004)Alec Stanculescu, Fintronic USA, 1304 Working Group past vice-chair(through June 2004)Stefen Boyd, Boyd Technology, ETF past co-chair(through November 2004)The following members of the entity balloting commitlee voted on this standard. Balloters may have votedfor approval, disapproval, or abstentionAccelleraIntel CorporationBluespec, Inc.Mentor Graphics CorporationCadence Dcsign Systcms, IncSun microsystems, IncIntronic u.s.aSunburst design, IncIBMSutherland hdl lncInfineon TechnologiesSynopsys, IncCopyright C 2006 IEEE. All rights reservedWhen the IEEE-SA Standards Board approved this standard on 8 November 2005, it had the followingmembershipSteve M. mills. chairRichard h. hulett vice chairDon wright Past chairJudith gorman. secretaryMark d. bowmanWilliam B HopfT W. olsenDennis B. BrophyLowell G. JohnsonGlenn parsonsJoseph brudeHerman KochRonald c. petersenRichard coxJoseph L. Koepfinger*Gary s. RobinsonBob davisDavid J lawFrank stoneJulian forster kDaleep c mohlaMalcolm v thadenJoanna n. gueninPaul nikolichRichard l. townsendS. HalpJoe d. watseRaymond hapemanHoward L, wolfmanAlso included are the following nonvoting Ieee-Sa Standards board liaisonsSatish K. aval, NRC RepresentativeRichard Deblasio, DOE RepresentativeAlan H. Cookson, NIST RepresentativeMichelle d, trIEEE Standards Project EditoCopyright C 2006 IEEE. All rights reservedContentsOverview1. 2 Conventions used in this standard1.3SIption1 4 Use of color in this standard1.5 Contents of this standard1.6 Deprecated clauses……….….….….…1.7 Header file listings....18 Examples…………………1.9PNormative references63. Lexical conventions83.1 Lexical tokens3.2 White space3. 3 Comments中··…·········:···············中·····“:·:·:·4·····“··········3. 4 Operators3. 5 Numberssteger constants3.5.2 Real constants123.5.3 Conversion123.6 Strings123.6. 1 String variable declaration133.6.2 String manipulation133.6.3 Special cha3.7 Identifiers. keds, and syste143.7.1 Escaped identifiers143.7.2 Keywords153.7.3 System tasks and functions3.7.4 Compiler directives153.8 Attrib163.8.1 Examples3.8.2 SyIata typ··4.1 Val214.2 Nets and variables4.2.1 Net declarations4.2.2 Variable declarations4.3V4.3.1g v244.3.2 Veclor net accessibility44.4 Strengths4.4.1 Charge strength4.4.2 Drive strength.....卓········中····“·········:·····················:········254.5 Implicit declarations4.6 Net types………264.6.1 Wire and tri nets264.6.2 Wired nets4.6.3TCopyright C 2006 IEEE. All rights reserved4.6.4 Trio and tri l nets4.6.5 Unresolved nets4.6.6 Supply nets324.7 Regs324.8 Integers, reals, times, and realtime4.8.1 Operators and real numbers4.8.2 Conversion4.9 Arrays4.9.1Net arrays…·中·····:··344.9.2 reg and variable arrays344.9.3 Memories4.10 Parameters…………………354.10.1 Module parameters…364.10.2 Local parameters(localparam““374.10.3 Specify parameters……384. Name spaces…39Expressions……5.1 Operators41Operators with real operands425.1.2 Operator precedence………5.1.3 Using integer numbers in expressions…….445.1.4 Expression evaluation order……2451. 5 Arithmetic operators5.1.6 Arithmetic expressions with regs and integers5. 1.7 Relational operators485.1.8Equ495.1.9 Logical operators…495.1.10 bitw isators505.1.11 Reduction operators5.112 Shift operators…….535. 1. 13 Conditional operator535.1. 14 Concatenations545.2 Operands………5.2. 1 Vector bit-Select and part-select addressing..565.2.2 Array and memory addressing.......,.……5.2.3ings585.3 Minimum, typical, and maximum delay expressions5.4 Expression bit lengths5.4.1 Rules for expression bit lengths65.4.2 Examole of expression bit-length problerpl635.4.3 Example of self-determined expressions.645.5 Signed expressions5.5.1 Rules for expression types.....5.5.2 Steps for evaluating5.5.3 Steps for evaluating an assignment5.54 Handling X and Z in signed expressions………5.6 Assignments and truncation6. Assignments……………686.1 Continuous assignments686. 1. 1 The net declaration assignment6.1.2 The continuous assignment statement·····中···:·:·4·中·····6.1.371Copyright C 2006 IEEE. All rights reserved

控制STM32F103输出两路互补的并带死区的PWM波，应用在MOSFET半桥或全桥控制

RS纠错编码原理及其实现方法。Zhengzhou Oriole Xinda Electronic Information Cc., Ltd前言随着越来越多的系统采用数字技术来实现,纠错编码技术也得到了越来越广泛的应用。RS码既可以纠正随机错误,又可以纠正突发错误,具有很强的纠错能力,在通信系统中应用广泛。近些年来,随着软件无线电技术的发展,RS编码、译码一般都在通用的硬件平台上实现。通常采用基于FPGA的ⅦHDL编码硬件实现,或者在DSP、单片机上用C和汇编编程软件实现。RS纠错编码涉及的领域很广,特别是设计到很多数学知识。这对那些对数学不太感冒的工程技术人员来书是个不小的挑战。尽管讲RS编码的书籍很多但是那些书都是采用循序渐进,逐步引人的方式从汉明码到循环码,从循环码到BCH码,BCH码再引入悶S码。对亍工程技术人员他们需要的是简明扼要的讲解,和详细的实现方法。本人写这篇文章的宗旨就是尽量最简单的语言最简短的篇幅来讲RS纠错编码原理,把重点来放在实现方法上。为了便于读者仿真,本文采样MLAB程序实现,程序尽量符合硬件C语言写法,读者经过简单修改即可应用到工程中去。本文读者对象本文是为那些初识瑙编码的学生、工程技术人员而写,并不适合做理论研究,如果你是纠错编码方面的学者、专家,那么本文并不适合你。由于作者水平有限,错误在所难免,恳请读者批评指正。不得更改陈文礼2008-01于郑州Zhengzhou Oriole Xinda Electronic Information Cc., Ltd必备的一些代数知识1、在纠错编码代数中,把以二进制数字表示的一个数据系列看成一个多项式。例如二进制数字序列1010111,可以表示成:M(x)=ax+a5x0+a5不5+a+4 TasK +ax+a,x+ank式中的x表示代码的位置,或某个二进制数位的位置,X前面的系数表示码的值。若a;是一位二进制代码,则取值是0或1。dM()称为信息代码多项式多项式次数称系数不为0的x的最高次数为多项式/(x)的次数,记为Of(x)2、域域在R编码理论中起着至关重要的作用。简单点说域GF(2)有2设2个符号[0,n,a2…22且具有以下性质域中的每个元素都可以用a",a,a2,om的和来表示。a←la为本原多项式p(x)的根。运算规则有:在纠错编码运算过程中,加减、乘和除的运算是在伽罗华域中进行。现以GF(2)域中运算为例:加法例:a+a=0010+0110101(模2加法相当于0005与011或减法运算与加法相同乘法例:a·a0=a(8+10)modl5除法例:cs/a0=a-2=a-2+5=a不理解没关系,下面的例子也许对你有帮助。例:mF=4,p(x)=x4+x+1求GF(2")的所有元素因为a为p(x)的根得到a4+a+1=0或a4=a+1(根据运算规则)Zhengzhou Oriole Xinda Electronic Information Cc., Ltd由此可以得到域的所有元素元素二进制对应十进制对应码值000000101000a+100l⊥0110a(a+1)=a+a(mod p(a))12a(a+a=a+a(mod p(a)1011a(a+l(modula))+a+1)10C(a+1=a+a(mod p(a )a(a23+a)a+I(mod p(a)1110a(a+a+D=aa+a(modp(a)tatI(mod p(a))11a(a3+a2+a+1)=a34a2+1(modp(a)1001a(a+a+1=a+l(mod p(a)a(a+1=l(mod(a))由此可以看岀本原多项式是求解域的全部元素的关键。读者也许会有这样的疑问我们如何得到p(x)呢?本原多城式p(x)的特性是2+得到的余式等于0O(X由于作者也是工程技术人员,具体怎么得到p(x),也没有深究过。Zhengzhou Oriole Xinda Electronic Information Cc., Ltd作者在设计RS编码时候都是根据 MATLAB指令rsgeηpoly来得到p(x)。其格式为 rsgenpoly(n,k)参数n为码长一般n=2"-1,k为信息码元个数。例如m4,码长n=15,信息码元长度为9GF(2)的本原多项式可以根据指令>>rsgenpoly(15, 9)得到ans= GF(2 4)array. Primitive polynomial =D 4+D+1 (19 decimal)有读者来信问:我要做一个(158的RS编码,在 MATLAB中输入命令 rsgenpoly(158,128),结果MAB报错Error using =- rsgenpolyN must equal 2m-1 for some integer m这里做一下解释我们S编码时普先要根据码长选取mλ选择原则是2若码长为6那么我们可以选择n=8, rsgenpey命令的第少个参数必须为2"-1,第二个参数司以随便选择只要小于2”-1就形了在此给出m∈(2,16)的所有本原多项式(m=2)P[m+1]={1,1,1}/米1+x+x3*/P[m+1]-{1,1,0,1}/米1+x+x4*/P[m11]={1,1,0,0,1}/米1+x2+x5*/P|m+1={1,0,1,0,0,1};Zhengzhou Oriole Xinda Electronic Information Cc., Ltd(m=6)/米1+x+x6*/P[m+1]={1,1,0,0,0,0,1}7)/来1+x3+x7*P[m+1]={1,0,0,1,0,0,0,1}(m=8)/米14x2+x31x4+x8*/P[m+1]-{1,0,1,1,1,0,0,0,1/*1+x4+x9半P[m1]={1,0,0,0,1,0,0,0,(m=10)/1+x3+x10*/P|m+1={1,0,0,1,0,0,0,0,/*1+x2+x11P[m+1]={1,0,0,0,0,0,0,1}(m=12)/*1+x+x4+x6+x12P[m+1]-{1,1,0,0,、1,0,0,(m=13)/*1+x+x^3+x4+x^13*/P[m+1]={1,1,0,1,1,0,0,00,0,1};(m=14)/*1+x+x6+x10+x14来P[m+1]={1,1,0,0,0,0,1,0,0,0,1,0,0,0,1}(m=15)/米14x+x15*/P[m+1]={1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,1};(m=16)/*1+x+x3+x12+x16*/P[m+1]={1,1,0,1,0,0,0,0,0,0,0,0,1,0,0,0,1};Zhengzhou Oriole Xinda Electronic Information Cc., Ltd二、线性分组码的一些基本概念1、线性分组码一般用(n,)或(n,k,d)表示n为码长,k为信息码元的数目,n-k为监督码元的数目。d表示码元距离。定义:两个码组上对应位置上数字不同的个数称为码组的距离。发送的码字C=(1,C2C3,…C接收的矢量r=(,2,信道错误图样:e=c+r例如c=(1,1,0,0,0)(1,0,001)e=(1+1,1+0,0+0,0+0,0+1)(0,1,0,0,1)从而可以看出从左端起第2位和第5位是错误的2、校验矩阵概念码长为n,信息数为k,监督数为r。这样的一组码形式为:m:m2,P,P2Pm表示第个信息码,P表示第j个校验码各个校验码可从下列线性方程组求得hm+h2m2+…+n+1B1+012+0h2m1+2m2+…+h2m+0p1p20hmn+h,2m2+…+hm+O+0+…+1p,=0式中h;是常数校验方程组可写成校验矩阵100h21h2…,h2k010h000该矩阵具有r行和n列故式(1-1)可以写成c=0或c=08Zhengzhou Oriole Xinda Electronic Information Cc., LtdH矩阵称为[n,k,r码的校验矩阵。发送矢量为C接收矢量为F若rH≠0则说明接收到的码有错误。设错误图样为e则可写成以下关系式r=c+e为了纠错必须知道那些位上存在错误。这可由校正子(又称伴随式)s来确定s=rH=cH +eh=eh译码器的主要任务就是如何从中得到最像e的错误图样e从而译出c=r-e设第讠个是错误的因此e=(00..0第个有错误s=rH=(00…0、100000)00计算出的矢量示出i是出错误的位置。3、生成矩阵概念生成矩阵G,它是一个k行,n列的矩阵若已知信息组m,通过生存矩阵可求得相应的码字。c=mxG(m是k个信息元组成的信息组)这个应该比较容易理解,在此就不做过多解释。、RS码的一些重要性质1、RS码生成多项式:码长n=2”-1,监督元数目r=n-k=2t,能纠正t个错误。Zhengzhou Oriole Xinda Electronic Information Cc., Ltd定义:在(n,k,d)的RS码中,存在唯一的n-k次多项式g(x),使得每一个码多项式c(x)都是g(x)的倍式。g(x)称为n,k,d]RS码的生成多项式一般情况下g(x)=(x-a)(x-a2)…(x-a2)2、定理:在GF(2m)中,每个非0元素(1,a,a2…a22)均满足x2=1,反之x21-1=0的根必在GF(2")中。所以x-1=(x-a)(x-a)x3、RS码的校验多项式由于生成多项式g(x)是x-1的因式g(rh(g(x)为n-k次多项式,则h(x)为k次多项式,k3x+g)hx+…+x+4)由右式可以看出x"1,x2,x的系数均等于0即gg0010h1+g1bo=0g0h+g1h11+…+8nkh2(2k)=0∴.+n-kk-10n-kk式中g0+81h1+…+8nkh1(n=k)(表示X的系数10