诛仙任务编辑器源码

Qt是一个跨平台的C++图形用户界面应用程序框架。它为应用程序开发者提供建立艺术级图形用户界面所需的所有功能。它是完全面向对象的，很容易扩展，并且允许真正的组件编程本资料采用PPT文档，共分23章详细介绍QT5技巧

成都光明2018年09月份，最新Zemax玻璃库

说明，这个matlab程序的目标是对BP神经网络中的神经元连接权和阈值构成的高维参数空间进行最优求解，试图用PSO算法求解神经网络中的参数，而不是用传统的误差反传算法。但由于经典粒子群算法存在局部最优的问题。该算法也存在同样的问题。该算法在迭代数较大时可以基本做到误差较大的函数拟合。但是通过该资源提供的图解和代码注释，用户可以很容易的学习到PSO算法的过程。至于如何突破局部最优，这个就有待各位PSO爱好者进行优化了。

基本粒子群算法，可以用来优化微电网调度问题，实现目标函数最小问题。

利用python相关技术搭建的用户画像web轻量级应用

光学自由曲面面形描述方法和光线追迹模型的研究

从国外网站找来的开源代码。飞利浦生命体征监护仪网络数据接口程序Demo，可直接运行，并从指定IP的监护仪上读取相关数据。配合对应的数据接口文档来理解更有帮助。也欢迎做同类项目的朋友一起交流。

申明：未经授权，本程序代码仅供研究参考，不得应用于任何商用场合。对复原图像振铃效应之一的边界振铃效应进行处理，本程序提供4种方法抑制因边界截断导致的边界振铃效应。参考文献：《基于振铃抑制的运动模糊图像复原方法研究》

The Verilog® Hardware Description Language (Verilog HDL) became an IEEE standard in 1995 as IEEEStd 1364-1995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in astandard textual format for a variety of design tools, including verification simulation, timiThe clear directive from the users for these three task forces was to start by solving some of the followingproblemsConsolidate existing IeeE Std 1364-1995Verilog generate statementMulti-dimensional arraysEnhanced Verilog file i/oRe-entrant tasksStandardize Verilog configurationsEnhance timing representationEnhance the vpi routinesAchievementsOver a period of four years the 1364 Verilog Standards Group(vsg) has produced five drafts of the lrmThe three task forces went through the EEe Std 1364-1995 lRM very thoroughly and in the process of consolidating the existing Lrm have been able to provide nearly three hundred clarifications and errata for theBehavioral, ASIC, and PLI sections. In addition, the vsg has also been able to agree on all the enhance-ments that were requested (including the ones stated above)Three new sections have been added. Clause 13, "Configuring the contents of a design, deals with configuration management and has been added to facilitate both the sharing of verilog designs between designersand/or design groups and the repeatability of the exact contents of a given simulation session Clause 15Timing checks, "has been broken out of Clause 17, "System tasks and functions, "and details more fullhow timing checks are used in specify blocks. Clause 16, "Backannotation using the Standard Delay Format(SDF), addresses using back annotation(IEEE Std 1497-1999)within IEEE Std 1364-2001Extreme care has been taken to enhance the vpi routines to handle all the enhancements in the behavioraland other areas of the lrm. minimum work has been done on the pli routines and most of the work hasbeen concentrated on the vpi routines. Some of the enhancements in the vpi are the save and restart simu-lation control, work area access, error handling, assign/deassign and support for array of instances, generateand file 1/0Work on this standard would not have been possible without funding from the cas society of the ieee andOpen verilog InternationalThe IEEE Std 1364-2001 Verilog standards Group organizationMany individuals from many different organizations participated directly or indirectly in the standardizationprocess. The main body of the Ieee Std 1364-2001 working group is located in the United States, with asubgroup in Japan (EIAJ/1364HDL)The members of the IEEE Std 1364-2001 working group had voting privileges and all motions had to beapproved by this group to be implemented the three task forces focused on their specific areas and theirrecommendations were eventually voted on by the Ieee Std 1364-2001 working group

流形学习中的LLE IOSMAP等8个算法，matlab编写