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FPGA_Based_CNN-master

于 2021-04-06 发布
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代码说明：

说明：  FPGA实现的CNN，使用verilog编程代码(CNN implemented by FPGA)

文件列表：

FPGA_Based_CNN-master\.gitignore, 188 , 2017-01-28
FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\.qsys_edit\filters.xml, 66 , 2017-01-28
FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\.qsys_edit\mem_system.xml, 82954 , 2017-01-28
FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\.qsys_edit\mem_system_schematic.nlv, 30976 , 2017-01-28
FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\.qsys_edit\pcie_system.xml, 83393 , 2017-01-28
FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\.qsys_edit\pcie_system_schematic.nlv, 0 , 2017-01-28
FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\.qsys_edit\preferences.xml, 534 , 2017-01-28
FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\avalon_bridge.v, 3012 , 2017-01-28
FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\avalon_bridge_hw.tcl, 8901 , 2017-01-28
FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\bit_width.vh, 341 , 2017-01-28
FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\cent_ctrl.v, 20130 , 2017-01-28
FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\cent_ctrl_hw.tcl, 14937 , 2017-01-28
FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\clock.v, 82 , 2017-01-28
FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\Clock_hw.tcl, 2326 , 2017-01-28
FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\cnn_parameters.vh, 837 , 2017-01-28
FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\conv.v, 15934 , 2017-01-28
FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\conv_old.v, 14910 , 2017-01-28
FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\db\DE5Net_Conv_Accelerator.db_info, 141 , 2017-01-28
FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\db\DE5Net_Conv_Accelerator.sld_design_entry.sci, 227 , 2017-01-28
FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\DE5Net_Conv_Accelerator.dpf, 1319 , 2017-01-28
FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\DE5Net_Conv_Accelerator.htm, 36760 , 2017-01-28
FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\DE5Net_Conv_Accelerator.qpf, 121 , 2017-01-28
FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\DE5Net_Conv_Accelerator.qsf, 43568 , 2017-01-28
FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\DE5Net_Conv_Accelerator.SDC, 6670 , 2017-01-28
FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\DE5Net_Conv_Accelerator.sld, 586 , 2017-01-28
FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\DE5Net_Conv_Accelerator.v, 75536 , 2017-01-28
FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\DE5Net_Conv_Accelerator_assignment_defaults.qdf, 54291 , 2017-01-28
FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\fifo_v2.qip, 428 , 2017-01-28
FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\fifo_v2.v, 6514 , 2017-01-28
FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\ifm_loader.v, 778 , 2017-01-28
FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\main_states.vh, 503 , 2017-01-28
FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\main_state_actions.v, 4501 , 2017-01-28
FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\main_state_machine.v, 3341 , 2017-01-28
FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\memory_export.v, 883 , 2017-01-28
FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\memory_export2.v, 2486 , 2017-01-28
FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\memory_export2_hw.tcl, 8206 , 2017-01-28
FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\memory_export_hw.tcl, 5704 , 2017-01-28
FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\mem_init.mif, 4488830 , 2017-01-28
FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\mem_system.qsys, 325795 , 2017-01-28
FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\mem_system.sopcinfo, 2830888 , 2017-01-28
FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\mem_system_mem_if_ddr3_emif_0_p0_all_pins.txt, 5938 , 2017-01-28
FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\mem_system_mem_if_ddr3_emif_0_p0_summary.csv, 2152 , 2017-01-28
FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\new_rtl_netlist, 205520 , 2017-01-28
FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\ofm_loader.v, 799 , 2017-01-28
FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\ofm_wb.v, 13569 , 2017-01-28
FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\old_rtl_netlist, 295410 , 2017-01-28
FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\parameters.vh, 231 , 2017-01-28
FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\pcie_system.qsys, 43280 , 2017-01-28
FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\pcie_system.sopcinfo, 2830802 , 2017-01-28
FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\pll_reconfig_xcvr_clk_src\pll_reconfig_xcvr_clk_src_0002.qip, 364 , 2017-01-28
FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\pll_reconfig_xcvr_clk_src\pll_reconfig_xcvr_clk_src_0002.v, 2092 , 2017-01-28
FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\pll_reconfig_xcvr_clk_src.qip, 65774 , 2017-01-28
FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\pll_reconfig_xcvr_clk_src.v, 17169 , 2017-01-28
FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\read_states.vh, 293 , 2017-01-28
FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\read_state_actions.v, 37946 , 2017-01-28
FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\rom_script.py, 1180 , 2017-01-28
FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\serv_req_info.txt, 6339 , 2017-01-28
FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\toSevenSeg.v, 659 , 2017-01-28
FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\weight_loader.v, 3922 , 2017-01-28
FPGA_Based_CNN-master\pcie_linux_driver\.altera_dma.ko.cmd, 323 , 2017-01-28
FPGA_Based_CNN-master\pcie_linux_driver\.altera_dma.mod.o.cmd, 27291 , 2017-01-28
FPGA_Based_CNN-master\pcie_linux_driver\.altera_dma.o.cmd, 41605 , 2017-01-28
FPGA_Based_CNN-master\pcie_linux_driver\.built-in.o.cmd, 200 , 2017-01-28
FPGA_Based_CNN-master\pcie_linux_driver\.goutputstream-0Y4HMY, 46011 , 2017-01-28
FPGA_Based_CNN-master\pcie_linux_driver\.goutputstream-2BLFMY, 45923 , 2017-01-28
FPGA_Based_CNN-master\pcie_linux_driver\.goutputstream-AXCMMY, 46682 , 2017-01-28
FPGA_Based_CNN-master\pcie_linux_driver\.goutputstream-O215MY, 58775 , 2017-01-28
FPGA_Based_CNN-master\pcie_linux_driver\.goutputstream-QK7EMY, 46674 , 2017-01-28
FPGA_Based_CNN-master\pcie_linux_driver\.goutputstream-QPOYMY, 95059 , 2017-01-28
FPGA_Based_CNN-master\pcie_linux_driver\.goutputstream-RQCNMY, 45828 , 2017-01-28
FPGA_Based_CNN-master\pcie_linux_driver\.tmp_versions\altera_dma.mod, 123 , 2017-01-28
FPGA_Based_CNN-master\pcie_linux_driver\altera.dma.hmc, 6007 , 2017-01-28
FPGA_Based_CNN-master\pcie_linux_driver\altera_dma.c, 63522 , 2017-01-28
FPGA_Based_CNN-master\pcie_linux_driver\altera_dma.cmc, 36147 , 2017-01-28
FPGA_Based_CNN-master\pcie_linux_driver\altera_dma.h, 8072 , 2017-01-28
FPGA_Based_CNN-master\pcie_linux_driver\altera_dma.ko, 31368 , 2017-01-28
FPGA_Based_CNN-master\pcie_linux_driver\altera_dma.ko.unsigned, 327253 , 2017-01-28
FPGA_Based_CNN-master\pcie_linux_driver\altera_dma.mod.c, 3189 , 2017-01-28
FPGA_Based_CNN-master\pcie_linux_driver\altera_dma.mod.o, 5744 , 2017-01-28
FPGA_Based_CNN-master\pcie_linux_driver\altera_dma.o, 28456 , 2017-01-28
FPGA_Based_CNN-master\pcie_linux_driver\altera_dma.tmp_c, 43167 , 2017-01-28
FPGA_Based_CNN-master\pcie_linux_driver\altera_dma_cmd.h, 2026 , 2017-01-28
FPGA_Based_CNN-master\pcie_linux_driver\altera_dma_load, 422 , 2017-01-28
FPGA_Based_CNN-master\pcie_linux_driver\built-in.o, 8 , 2017-01-28
FPGA_Based_CNN-master\pcie_linux_driver\genRandData.py, 178 , 2017-01-28
FPGA_Based_CNN-master\pcie_linux_driver\install, 105 , 2017-01-28
FPGA_Based_CNN-master\pcie_linux_driver\Makefile, 355 , 2017-01-28
FPGA_Based_CNN-master\pcie_linux_driver\Module.symvers, 0 , 2017-01-28
FPGA_Based_CNN-master\pcie_linux_driver\modules.order, 69 , 2017-01-28
FPGA_Based_CNN-master\pcie_linux_driver\README, 211 , 2017-01-28
FPGA_Based_CNN-master\pcie_linux_driver\run, 74 , 2017-01-28
FPGA_Based_CNN-master\pcie_linux_driver\unload, 46 , 2017-01-28
FPGA_Based_CNN-master\pcie_linux_driver\user\.goutputstream-2414NY, 16956 , 2017-01-28
FPGA_Based_CNN-master\pcie_linux_driver\user\.goutputstream-8WEYNY, 14407 , 2017-01-28
FPGA_Based_CNN-master\pcie_linux_driver\user\.goutputstream-MHRGMY, 11818 , 2017-01-28
FPGA_Based_CNN-master\pcie_linux_driver\user\user, 18088 , 2017-01-28
FPGA_Based_CNN-master\pcie_linux_driver\user\user.c, 19715 , 2017-01-28
FPGA_Based_CNN-master\README.md, 1513 , 2017-01-28
FPGA_Based_CNN-master\Using the User Application.pdf, 161097 , 2017-01-28
FPGA_Based_CNN-master\DE5Net_Conv_Accelerator\.qsys_edit, 0 , 2020-10-06

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