matlab时频分析及其应用--pdf

PPT中详细的介绍了使用latex进行论文撰写的必要；使用latex插入图片、公式、表格的方法；及重要的排版技巧等。对准备发表IEEE论文及其它外刊论文的同学、同行有很好的参考价值。

气象统计EOF的MATLAB程序，可以直接使用，比较容易看懂的

使用matlab实现科斯塔斯环的同步，利用本地初始频率和科斯塔斯环，经过多次迭代后，使最后获得的载波频率趋近于实际发送信号的载波频率

图像处理所用的标准测试图像，512*512的灰度图，包括：lena,aerial,airfield,baboon,barbara,blonde,boat,bridge,cameraman,couple,darkhair,dollar,fingerprint,goldhill,lake,peppers,priate,plane,yacht。共计19副图像，位深度为8.

这是关于用MATLAB编写M文件求复合材料层合板性能指标的一个作业，第一个M文件是对层合板性能的分析，第二个M文件是对层合板破坏的分析。

对一个产生的离散序列作傅立叶变换，分析其频率响应特性（给出幅频与相频特性曲线）-A discrete sequence generated for the Fourier transform to analyze the frequency response characteristics (frequency and amplitude given phase frequency response curve)

适合研究水声通信的同学，里面介绍的很详细，希望能对大家有帮助

一个java程序，适合与新手入门，gui程序，结合mysql数据库，类似美团，淘宝的点餐平台

The Verilog® Hardware Description Language (Verilog HDL) became an IEEE standard in 1995 as IEEEStd 1364-1995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in astandard textual format for a variety of design tools, including verification simulation, timiThe clear directive from the users for these three task forces was to start by solving some of the followingproblemsConsolidate existing IeeE Std 1364-1995Verilog generate statementMulti-dimensional arraysEnhanced Verilog file i/oRe-entrant tasksStandardize Verilog configurationsEnhance timing representationEnhance the vpi routinesAchievementsOver a period of four years the 1364 Verilog Standards Group(vsg) has produced five drafts of the lrmThe three task forces went through the EEe Std 1364-1995 lRM very thoroughly and in the process of consolidating the existing Lrm have been able to provide nearly three hundred clarifications and errata for theBehavioral, ASIC, and PLI sections. In addition, the vsg has also been able to agree on all the enhance-ments that were requested (including the ones stated above)Three new sections have been added. Clause 13, "Configuring the contents of a design, deals with configuration management and has been added to facilitate both the sharing of verilog designs between designersand/or design groups and the repeatability of the exact contents of a given simulation session Clause 15Timing checks, "has been broken out of Clause 17, "System tasks and functions, "and details more fullhow timing checks are used in specify blocks. Clause 16, "Backannotation using the Standard Delay Format(SDF), addresses using back annotation(IEEE Std 1497-1999)within IEEE Std 1364-2001Extreme care has been taken to enhance the vpi routines to handle all the enhancements in the behavioraland other areas of the lrm. minimum work has been done on the pli routines and most of the work hasbeen concentrated on the vpi routines. Some of the enhancements in the vpi are the save and restart simu-lation control, work area access, error handling, assign/deassign and support for array of instances, generateand file 1/0Work on this standard would not have been possible without funding from the cas society of the ieee andOpen verilog InternationalThe IEEE Std 1364-2001 Verilog standards Group organizationMany individuals from many different organizations participated directly or indirectly in the standardizationprocess. The main body of the Ieee Std 1364-2001 working group is located in the United States, with asubgroup in Japan (EIAJ/1364HDL)The members of the IEEE Std 1364-2001 working group had voting privileges and all motions had to beapproved by this group to be implemented the three task forces focused on their specific areas and theirrecommendations were eventually voted on by the Ieee Std 1364-2001 working group

前面传上来的学生学籍管理系统论文只能传一个，所以这里再把相应的答辩ppt上传上来供大家下载。