蚁群算法解决旅行商问题（Matlab版）

The Verilog® Hardware Description Language (Verilog HDL) became an IEEE standard in 1995 as IEEEStd 1364-1995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in astandard textual format for a variety of design tools, including verification simulation, timiThe clear directive from the users for these three task forces was to start by solving some of the followingproblemsConsolidate existing IeeE Std 1364-1995Verilog generate statementMulti-dimensional arraysEnhanced Verilog file i/oRe-entrant tasksStandardize Verilog configurationsEnhance timing representationEnhance the vpi routinesAchievementsOver a period of four years the 1364 Verilog Standards Group(vsg) has produced five drafts of the lrmThe three task forces went through the EEe Std 1364-1995 lRM very thoroughly and in the process of consolidating the existing Lrm have been able to provide nearly three hundred clarifications and errata for theBehavioral, ASIC, and PLI sections. In addition, the vsg has also been able to agree on all the enhance-ments that were requested (including the ones stated above)Three new sections have been added. Clause 13, "Configuring the contents of a design, deals with configuration management and has been added to facilitate both the sharing of verilog designs between designersand/or design groups and the repeatability of the exact contents of a given simulation session Clause 15Timing checks, "has been broken out of Clause 17, "System tasks and functions, "and details more fullhow timing checks are used in specify blocks. Clause 16, "Backannotation using the Standard Delay Format(SDF), addresses using back annotation(IEEE Std 1497-1999)within IEEE Std 1364-2001Extreme care has been taken to enhance the vpi routines to handle all the enhancements in the behavioraland other areas of the lrm. minimum work has been done on the pli routines and most of the work hasbeen concentrated on the vpi routines. Some of the enhancements in the vpi are the save and restart simu-lation control, work area access, error handling, assign/deassign and support for array of instances, generateand file 1/0Work on this standard would not have been possible without funding from the cas society of the ieee andOpen verilog InternationalThe IEEE Std 1364-2001 Verilog standards Group organizationMany individuals from many different organizations participated directly or indirectly in the standardizationprocess. The main body of the Ieee Std 1364-2001 working group is located in the United States, with asubgroup in Japan (EIAJ/1364HDL)The members of the IEEE Std 1364-2001 working group had voting privileges and all motions had to beapproved by this group to be implemented the three task forces focused on their specific areas and theirrecommendations were eventually voted on by the Ieee Std 1364-2001 working group

win7下运行k3 远程组件注册 出错，无法使用k3，及报表系统 提示KDSpreadU.ocx不能注册的解决方法，经win7+k310.3sp1客户端环境成功。

我自己原创的用verilog hdl语言编写的一个(7,3)循环码的编码器.文件压缩包中除了有.v的源文件外,还把在maxplusII下仿真波形图的文件也包括进去了,供网友参考.仿真中输入了两个信息码字分别是"011"和"101".生成多项式采用的是x^4+x^3+x^2+1

《Ray Tracing in One Weekend》Peter Shirley 的书2016版，非常好的光线追踪入门教材，包括 pdf 文件以及两份 c++源码

【实例简介】自制有源高速光耦隔离RS232转RS485 RS422的电路图

这是大学本科生毕业设计作品 课题题目为基于JSP的小型旅游网站 该网站是以一旅行社为基准 面向网络中的所有客户 为其提供服务的小型旅游网站 已完成了网站的所有基础内容 该资源内有源代码 毕业设计论文 在论文中有详细的数据库建表过程 只需稍加修改即可使用 为了查重安全 也可选择其中有用的内容 该作品在大学中的毕业设计成绩为良 希望这个作品可以为您提供有用的帮助 也可以对其进行改进 谢谢！

PCNN分割，边缘提取，图像增强等matlab程序，比较全面简单的源代码，易看易懂易学

数学辞海（第六卷 Vol6）(全六卷) by 裘光明等 数学辞海编辑委员会.pdf

【实例简介】常规的空时自适应处理，可有效抑制杂波和干扰。

WSN中质心定位算法和基于移动锚节点的定位算法研究