Verilog-IEEE Std 1364 -2005 IEEE Standard
Verilog的IEEE标准，比较新的一个吧应该是IEEE Std 1364 TM-2005(Revision of IEEE Std 1364-2001)lEE Standard for VerilogHardware Description LanguageSponsorDesign Automation Standards Committeeof theIEEE Computer SocietyAbstract: The Verilog hardware description language(HDL) is defined in this standard. VerilogHDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine-readable and human-readable, it supports the development, verificationsynthesis, and testing of hardware designs; the communication of hardware design data; and themaintenance, modification, and procurement of hardware. The primary audiences for this standardare the implementors of tools supporting the language and advanced users of the languageKeywords: computer, computer languages, digital systems, electronic systems, hardware, hardware description languages, hardware design, HDL, PLI, programming language interface, Verilog,Verilog HDL, verilog PllThe Institute of Electrical and Electronics Engineers, Inc3 Park Avenue. New york. NY 10016-5997 USACopyright@ 2006 by the Institute of Electrical and Electronics Engineers, IncAll rights reserved Published 7 April 2006. Printed in the United states of AmericaIEEE is a registered trademark in the U.S. Patent Trademark Office, owned by the Institute of Electrical and ElectronicsEngineers, IncorporatedVerilog is a registered trademark of Cadence Design Systems, IncPrint:|sBN0-738148504SH95395PDFSBN0-7381-48512SS95395No part of this publication may be reproduced in any form, in an electronic retrieval system or otherwise, without the priorwritten permission of the publisher.IEEE Standards documents are developed within the IEee Societies and the Standards CoordinatingCommittees of the iEEE Standards Association (IEEE-SA)Standards board The ieee develops its standardsthrough a consensus development process, approved by the american National Standards Institute, which bringstogether volunteers representing varied viewpoints and interests to achieve the final product. Volunteers are notnecessarily members of the Institute and serve without compensation. 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Suggestions for changes in documents should be in the form of a proposed change of texttogether with appropriate supporting comments Comments on standards and requests for interpretations shouldaddressed toIEEE-SA Standards Board445 Hoes lanePiscataway, NJ 08854USANoTE-Attention is called to the possibility that implementation of this standard may require use of subjectmatter covered by patent rights. By publication of this standard, no position is taken with respect to theexistence or validity of any patent rights in connection therewith. The IEf shall not be responsible foridentifying patents for which a license may be required by an ieee standard or for conducting inquiries into thelegal validity or scope of those patents that are brought to its attentionAuthorization to photocopy portions of any individual standard for internal or personal use is granted by the Institute of Electrical and Electronics Engineers, Inc, provided that the appropriate fee is paid to Copyright ClearanceCenter. To arrange for payment of licensing fee, please contact Copyright Clearance Center, Customer Service222 Rosewood Drive, Danvers, MA01923 USA; +19787508400. Permission to photocopy portions of any indi-idual standard for educational classroom use can also be obtained through the Copyright Clearance CenterIntroductionThis introduction is not a part of IEEE Std 1364-2005, IEEE Standard for Verilog Hardware Description LanguageThe Verilog hardware description language(HDL) became an IEEE standard in 1995 as IEEE Std 13641995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in a standardtextual format for a variety of design tools, including verification simulation, timing analysis, test analysisand synthesis. It is because of these rich features that verilog has been accepted to be the language of choiceby an overwhelming number of integrated circuit(IC)designersVerilog contains a rich set of built-in primitives, including logic gates, user-definable primitives, switches,and wired logic. It also has device pin-to-pin delays and timing checks. The mixing of abstract levels isessentially provided by the semantics of two data types: nets and variables. Continuous assignments, inwhich expressions of both variables and nets can continuously drive values onto nets, provide the basicstructural construct. Procedural assignments, in which the results of calculations involving variable and netvalues can be stored into variables, provide the basic behavioral construct. a design consists of a set of modules, each of which has an input/output(1/O)interface, and a description of its function, which can be structural, behavioral, or a mix. These modules are formed into a hierarchy and are interconnected with netsThe Verilog language is extensible via the programming language interface(PLI)and the verilog procedural interface(VPi) routines. The Pli/vPi is a collection of routines that allows foreign functions to accessinformation contained in a Verilog hdl description of the design and facilitates dynamic interaction withsimulation. Applications of PLI/VPI include connecting to a Verilog HDL simulator with other simulationand computer-assisted design(CAD)systems, customized debugging TaskS, delay calculators, andannotatorsThe language that influenced Verilog HDL the most was HILO-2, which was developed at Brunel University in England under a contract to produce a test generation system for the British Ministry of DefensehiLO-2 successfully combined the gate and register transfer levels of abstraction and supported verificationsimulation, timing analysis, fault simulation, and test generationIn 1990, Cadence Design Systems placed the Verilog HDL into the public domain and the independentOpen Verilog International(oVi)was formed to manage and promote Verilog HDL. In 1992, the Board ofDirectors of ovi began an effort to establish Verilog hdl as an ieeE standard. In 1993, the first IEeEworking group was formed; and after 18 months of focused efforts, Verilog became an IEEE standard asIEEE Std 1364-1995After the standardization process was complete, the IEEe P1364 Working Group started looking for feedback from IEEE 1364 users worldwide so the standard could be enhanced and modified accordingly. Thisled to a five-year effort to get a much better Verilog standard in IEEE Std 1364-2001With the completion of IEEE Std 1364-2001, work continued in the larger Verilog community to identifyoutstanding issues with the language as well as ideas for possible enhancements. As Accellera began work-ing on standardizing System Verilog in 2001, additional issues were identified that could possibly have led toincompatibilities between Verilog 1364 and System Verilog. The IEEE P1364 Working group was established as a subcomittee of the System Verilog P1800 Working Group to help ensure consistent resolution ofsuch issues. The result of this collaborative work is this standard ieee Std 1364-2005Copyright C 2006 IEEE. All rights reservedNotice to usersErrataErrata,ifanyforthisandallotherstandardscanbeaccessedatthefollowingurL:http:/stan-dards.ieee.org/reading/ieee/updates/errata/index.html. Users are encouraged to check this URL for errataperiodicaInterpretationsCurrentinterpretationscanbeaccessedatthefollowingUrl:http:/standards.ieeeorg/reading/ieee/interp/Index. htmlPatentsAttention is called to the possibility that implementation of this standard may require use of subject mattercovered by patent rights. By publication of this standard, no position is taken with respect to the existence orvalidity of any patent rights in connection therewith. The IEee shall not be responsible for identifyingpatents or patent applications for which a license may be required to implement an IEEE standard or forconducting inquiries into the legal validity or scope of those patents that are brought to its attentionParticipantsAt the time this standard was completed, the ieee P1364 Working group had the following membershipJohny Srouji, IBM, IEEE SyStem verilog Working Group chairTom Fitzpatrick, Mentor Graphics Corporation, ChairNeil Korpusik, Sun Microsystems, Inc, Co-chairStuart sutherland sutherland hdl inc. editorShalom Bresticker, Intel Corporation, Editor through February 2005The Errata Task Force had the following membershipKaren pynopsys,rKurt baty. WFSDB ConsultinDennis marsa. XilinxStefen Boyd, Boyd TechnologyFrancoise Martinolle, Cadence Design Systems, IncShalom Bresticker, Intel CorporationMike McNamara, Verisity, LtdDennis Brophy, Mentor Graphics CorporationDon Mills, LCDM EngineeringCliff Cummings, Sunburst Design, IncAnders nordstrom, Cadence Design Systems, IncCharles dawson, Cadence Design Systems, IncKaren Pieper, Synopsys, IncTom Fitzpatrick, Mentor Graphics CorpoBrad Pierce, Synopsys, IncRonald goodstein, first shot Logic simulation andSteven Sharp Cadence Design Systems, IncAlec Stanculescu. Fintronic USA IncDesignStuart Sutherland. Sutherland HDL IncMark Hartog, Synopsys incGordon Vreugdenhil, Mentor Graphics CorporationJames Markevitch, Evergreen Technology GroupJason Woolf, Cadence design Systems, IncCopyright C 2006 IEEE. All rights reservedThe behavioral Task Force had the following membership:Steven Sharp, Cadence Design Systems, InC, ChairKurt Baty, WFSDB ConsultingJay lawrence. Cadence design Systems. IncStefen Boyd, Boyd TechnologyFrancoise Martinolle, Cadence Design Systems, IncShalom Bresticker, Intel CorporationKathryn McKinley, Cadence Design Systems, IncDennis brophy, Mentor graphics corporationMichael mcnamara. Verisity LtdCliff Cummings, Sunburst Design, IncDon Mills, LCDM EngineeringSteven Dovich, Cadence Design Systems, IncMehdi Mohtashemi, Synopsys, IncTom Fitzpatrick, Mentor Graphics CorporationKaren Pieper, Synopsys, IncRonald Goodstein, First Shot Logic Simulation andBrad Pierce, Synopsys, IncDesignDave Rich, Mentor Graphics CorporationKeith Gover, Mentor Graphics CorporationSteven Sharp, Cadence Design Systems, IncMark Hartoog, Synopsys, IncAlec Stanculescu. Fintronic USAEnnis Hawk, Jeda TechnologiesStuart Sutherland. Sutherland hdl. IncAtsushi kasuya, Jcda TechnologicsGordon Vrcugdcnhil, Mentor Graphics CorporationThe PLI Task Force had the following membershipCharles Dawson, Cadence Design Systems, Inc, ChairGhassan Khoory, Synopsys, Inc Co-chairTapati Basu, Synopsys, IncMichael rohleder. Freescale Semiconductor. IncSteven Dovich, Cadence Design Systems, IncRob Slater, Freescale Semiconductor IncRalph duncan, Mentor Graphics CorporationJohn Stickley, Mentor Graphics CorporationJim garnett, Mentor Graphics CorporationStuart Sutherland. Sutherland HDL. incJoao geada CLK Design AutomationBassam Tabbara. Novas software. IncAndrzej litwiniuk, Synopsys, IncJim Vellenga, Cadence Design Systems, IncFrancoise Martinolle, Cadence Design Systems, IncDoug Warmke, Mentor Graphics CorporationSachchidananda Patel, Synopsys, IncIn addition, the working group wishes to recognize the substantial efforts of past contributorsMichael McNamara, Cadence Design Systems, Inc1364 Working Group past chair(through September 2004)Alec Stanculescu, Fintronic USA, 1304 Working Group past vice-chair(through June 2004)Stefen Boyd, Boyd Technology, ETF past co-chair(through November 2004)The following members of the entity balloting commitlee voted on this standard. Balloters may have votedfor approval, disapproval, or abstentionAccelleraIntel CorporationBluespec, Inc.Mentor Graphics CorporationCadence Dcsign Systcms, IncSun microsystems, IncIntronic u.s.aSunburst design, IncIBMSutherland hdl lncInfineon TechnologiesSynopsys, IncCopyright C 2006 IEEE. All rights reservedWhen the IEEE-SA Standards Board approved this standard on 8 November 2005, it had the followingmembershipSteve M. mills. chairRichard h. hulett vice chairDon wright Past chairJudith gorman. secretaryMark d. bowmanWilliam B HopfT W. olsenDennis B. BrophyLowell G. JohnsonGlenn parsonsJoseph brudeHerman KochRonald c. petersenRichard coxJoseph L. Koepfinger*Gary s. RobinsonBob davisDavid J lawFrank stoneJulian forster kDaleep c mohlaMalcolm v thadenJoanna n. gueninPaul nikolichRichard l. townsendS. HalpJoe d. watseRaymond hapemanHoward L, wolfmanAlso included are the following nonvoting Ieee-Sa Standards board liaisonsSatish K. aval, NRC RepresentativeRichard Deblasio, DOE RepresentativeAlan H. Cookson, NIST RepresentativeMichelle d, trIEEE Standards Project EditoCopyright C 2006 IEEE. All rights reservedContentsOverview1. 2 Conventions used in this standard1.3SIption1 4 Use of color in this standard1.5 Contents of this standard1.6 Deprecated clauses……….….….….…1.7 Header file listings....18 Examples…………………1.9PNormative references63. Lexical conventions83.1 Lexical tokens3.2 White space3. 3 Comments中··…·········:···············中·····“:·:·:·4·····“··········3. 4 Operators3. 5 Numberssteger constants3.5.2 Real constants123.5.3 Conversion123.6 Strings123.6. 1 String variable declaration133.6.2 String manipulation133.6.3 Special cha3.7 Identifiers. keds, and syste143.7.1 Escaped identifiers143.7.2 Keywords153.7.3 System tasks and functions3.7.4 Compiler directives153.8 Attrib163.8.1 Examples3.8.2 SyIata typ··4.1 Val214.2 Nets and variables4.2.1 Net declarations4.2.2 Variable declarations4.3V4.3.1g v244.3.2 Veclor net accessibility44.4 Strengths4.4.1 Charge strength4.4.2 Drive strength.....卓········中····“·········:·····················:········254.5 Implicit declarations4.6 Net types………264.6.1 Wire and tri nets264.6.2 Wired nets4.6.3TCopyright C 2006 IEEE. All rights reserved4.6.4 Trio and tri l nets4.6.5 Unresolved nets4.6.6 Supply nets324.7 Regs324.8 Integers, reals, times, and realtime4.8.1 Operators and real numbers4.8.2 Conversion4.9 Arrays4.9.1Net arrays…·中·····:··344.9.2 reg and variable arrays344.9.3 Memories4.10 Parameters…………………354.10.1 Module parameters…364.10.2 Local parameters(localparam““374.10.3 Specify parameters……384. Name spaces…39Expressions……5.1 Operators41Operators with real operands425.1.2 Operator precedence………5.1.3 Using integer numbers in expressions…….445.1.4 Expression evaluation order……2451. 5 Arithmetic operators5.1.6 Arithmetic expressions with regs and integers5. 1.7 Relational operators485.1.8Equ495.1.9 Logical operators…495.1.10 bitw isators505.1.11 Reduction operators5.112 Shift operators…….535. 1. 13 Conditional operator535.1. 14 Concatenations545.2 Operands………5.2. 1 Vector bit-Select and part-select addressing..565.2.2 Array and memory addressing.......,.……5.2.3ings585.3 Minimum, typical, and maximum delay expressions5.4 Expression bit lengths5.4.1 Rules for expression bit lengths65.4.2 Examole of expression bit-length problerpl635.4.3 Example of self-determined expressions.645.5 Signed expressions5.5.1 Rules for expression types.....5.5.2 Steps for evaluating5.5.3 Steps for evaluating an assignment5.54 Handling X and Z in signed expressions………5.6 Assignments and truncation6. Assignments……………686.1 Continuous assignments686. 1. 1 The net declaration assignment6.1.2 The continuous assignment statement·····中···:·:·4·中·····6.1.371Copyright C 2006 IEEE. All rights reserved
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物流网络选址与路径优化问题的模型与启发式解法
物流网络选址与路径优化问题的模型与启发式解法120交通运输工程学报2006年(i∈T)(10表1小规模问题的计算结果Tab. 1 Computation result of smalF-scaled problem(xh+xbk)-z≤1(i∈T,∈Ck∈K)(11)最优解∈TUC(j∈C问题规模目标值运行时间/s(12)NG= 3, NT=3, Nc= 83885k≤s1(≤c1121=∑体k∈(13NG=3,Nr=3,Nc=10421.221U-U+Nx≤N-1(i,∈S,k∈K)(14)NG=3,Nr=3,Nc=126850580∈TNG=3,NT=3,Nc=148741162000注:Nc为供应商数量,Nr为配送中心数量,Nc为客户数量ba≤B(g∈G)(16用启发式算法求得初期解xi∈/Q1(i,j∈T∪C,k∈K)(17)l0;∈/0,1∈T(18通过交换配送中心间的路径进行第1次解的改善∈/O,1∈T,j∈C)(19)yk∈/0,1(i∈C,k∈K)(20)通过交换同一路径中客户的位置(2-OPT法)进行第2次解的改善式中:G为供应商的集合;T为配送中心的集合;C为客户的集合;K为车辆的集合;Qk为车辆k的最通过交换不同路径中的客户进行第3次解的改善大载质量:S为C的部分集合;C为从点到点j的距离;B为供应商g的最大供应量;V为配送中心SA模块的最大货物通过量;D,为客户j的需求量;H2为配送中心i的固定费用;L为从供应商g到配送中是否满足终止条件心i的单位运输费用;Fk为车辆k的固定费用;a为解的输出与通过量有关的系数;xk为对于车辆k,如果点i以后的访问点是点j,即为1,否则为0;y为如果点j图1基于SA的混合启发式算法的货物由车辆k配送,即为1,否则为0;v;为如果FiMixed heuristic algorit hm based on sa使用配送中心i,即为1,否则为0;z为如果客户j传统启发式算法与智能启发式算法相结合的混合算由配送中心提供服务,即为1,否则为0;pa为从供法,以期在短时间内求得全局最优解应商g到配送中心的供应量。其中x、3计算分析和pg为决策变量。2问题的求解为了对SA的参数进行设定,进行了预备实验并确定参数如下:初始温度To为200冷却率α为为了验证上述数学模型的正确性,用数理规划07,与温度相关的循环次数调整参数β为.1,最商用软件 LINGO8.0对小规模问题进行了数值计大循环次数将按照问题规模的大小做适当的设定,算,结果见表1。可以看出,随着问题的规模扩大,数据采用人工生成数据,在200km×200km的区计算时间急剧增加;当客户达到14个时,计算时间域内随机生成指定个数的供应商、配送中心和客户,长达45h,显然无法满足解决现实问题的需要。为并生成距离矩阵和客户需求量;采用C语言编程,了满足解决现实问题的需要,有必要开发岀一种能计算结果见表2。从表2中的结果比较可以看出,够在合理的时间内求得准最优解的近似算法。表2最优解与近似解比较传统启发式算法能够在短时间内求得局部最优Tab 2 Comparison of optimal solution and approxi mate solution解,但往往容易陷于局部最优,而无法求得全局最优最优解近似解问题规模解。智能启发式算法能够求得全局最优解,但计算时目标值运行时间/s目标值运行时间/s%间相对较长。如果能够将两者结合起来,既可以防止N=3N=3,Nc=838533965求解过程陷于局部搜索无法跳出,保证全局解的搜3N=3NG=10+2122112100索,又可以缩短搜索时间达到在短时间内求得全局N-3-3Nc12|60s0620110最优解的目的。基于上述考虑本文提出了图1的将ublishrigfoustAingnsestrvcu,trttp/www.urrhi.rctNG=3,Nr=3,Nc=1487411620008895第3期陈松岩,等:物流网络选址与路径优化问题的模型与启发式解法121本算法求得的近似解与 LINGO80计算的最优解心,再从配送中心到客户这一典型的物流过程,涉及之间的误差很小,但计算时间却大大缩短了。依据运输与配送2个阶段和供应商、配送中心和客户3结果虽然无法判定所提岀的混合启发式算法对于大个层次,提出了多供应商、多物流中心情况下的物流规模问题的有效性,但可以看岀,对于求解小规模问路径与配送路径优化问题,给岀了问题的数学模型,题是有效和良好的。对于大规模问题,将利用实例利用传统启发式算法与模拟退火法开发了混合近似进行计算验证。解法,通过人工生成数据和实例计算验证,可以看出4应用实例所提出的数学模型可以准确地描述此类问题,具有良好的适应性,所提出的混合近似解法能够在短时在应用实例中,将港口作为供应商来考虑,以进间内求解问题并得到接近于最优解的近似解,具有口货物从港口经配送中心配送到客户过程中发生的较高的实用价值。但本模型没有考虑库存问题与供费用最小化为目的,以港口的数量和位置、配送中心应商的成本问题,无法达到物流网络中各个环节的数量和位置作为对象进行优化。实例的区域选择山整体优化,有待于今后进一步研究。东省,候选港口为天津港、烟台港、威海港、青岛港参考文献日照港和连云港等6处,候选配送中心设置于山东省除港口城市以外的13个地级市,设定客户分别位References于90个县(包括县级市)。为了分析候选港口和配1 I anen g Flpo C. Spatial de composit ion for a multI送中心的数量及位置与目标值之间的关系,在计算of Production Economics, 2000, 64(1/2/3): 177186过程中,候选港口和配送中心的数量分别从1开始(21 Melkote s, Das kin m s. a n in te grated model of facil ity loca tion增加(港口的位置为随机选择),计算结果见图2、3and transportat ion netw ork design[ J. Transport ation Research part A,2001,35(6):5155386[3] Goets chalckx M, Vidal C J Dogan K Modeling and design ofglobal logistics s yst ems: a review of integrated strat e gic an dt act ical models and design algorithm s[ J European Journal of005◇◇0◇◇◇◇◇◇◇Operat ional Research, 2002, 143 (1):118135791113[4] H wang H S Design of suppl y chain logist ics sy stem con sider-港口数量配送中心数量ing service level[ J. Computers and Industrial Engineerin g,图2港口数量与图3配送中心数量与2002,43(1/2):283297目标函数值关系目标函数值关系[5] WuT H, Low C, Bai J W. Heurist ic s ol ution s to mu ltt depotFig2 Relation of ob ject value Fig 3 Relation of ob ject valuelocatioN rou tin g pr ob lems[ J]. Computers and Operations Re-and ports numberand changing depots num besearch,2002,29(10):13931415可以看出,随着候选港口数量的增加.目标值呈[6 Syam ss. A model and met hodologies for the locat ion p rob lem下降趋势,说明可供选择的港口越多,求得最优解的with logist ical components[ J]. Computers and Operations Re机会越大,但本例中,当候选港口的数量增加到5个se arch,200)2,29(9):l173-1193时,目标值达到最小(实际被选中的港口为3个);候[7 Amiri A. Designing a distribution network in a suppl y chainsystem[ J]. European Jou rnal of O perat ional Research, 2004选配送中心数量的变化也呈相同的趋势,当候选配171(2):567576送中心数量达到9个时,目标值达到最小(实际被选8 G ena m, Syarif a. Hybrid genetic algorit hm for mult+ time pe-中的配送中心为8个);本实例的计算时间都在8sriod production/ distribution planning[ J1. Computers and Ir以内,虽然无法判断所求解为最优解,但从计算结果dustrial Engineering, 2005, 48(4): 799809来看,基本接近最优,因此可以认为本算法对于求解9工丰元,潘福全张丽霞等基于交通限制的路网最优路径算大规模问题也是有效和良好的法J.交通运输工程学报,2005,5(1):9295Wang Feng yuan, Pan Fuquan, Zhang Li xia, et al. Opti mal5结语path algorithm of road netw ork with traffic rest riction[ JIJourn al of Traffic and Trans port ation Engin eering, 2005, 5(1)本文将研究范围界定在商品从供应商到配送中9295.(in Ch ineseo1994-2012ChinaacAdemicJournalElectronicPublishingHouse.Allrightsreservedhttp://www.cnki.net
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