Verilog-IEEE Std 1364 -2005 IEEE Standard
Verilog的IEEE标准，比较新的一个吧应该是IEEE Std 1364 TM-2005(Revision of IEEE Std 1364-2001)lEE Standard for VerilogHardware Description LanguageSponsorDesign Automation Standards Committeeof theIEEE Computer SocietyAbstract: The Verilog hardware description language(HDL) is defined in this standard. VerilogHDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine-readable and human-readable, it supports the development, verificationsynthesis, and testing of hardware designs; the communication of hardware design data; and themaintenance, modification, and procurement of hardware. The primary audiences for this standardare the implementors of tools supporting the language and advanced users of the languageKeywords: computer, computer languages, digital systems, electronic systems, hardware, hardware description languages, hardware design, HDL, PLI, programming language interface, Verilog,Verilog HDL, verilog PllThe Institute of Electrical and Electronics Engineers, Inc3 Park Avenue. New york. NY 10016-5997 USACopyright@ 2006 by the Institute of Electrical and Electronics Engineers, IncAll rights reserved Published 7 April 2006. Printed in the United states of AmericaIEEE is a registered trademark in the U.S. Patent Trademark Office, owned by the Institute of Electrical and ElectronicsEngineers, IncorporatedVerilog is a registered trademark of Cadence Design Systems, IncPrint:|sBN0-738148504SH95395PDFSBN0-7381-48512SS95395No part of this publication may be reproduced in any form, in an electronic retrieval system or otherwise, without the priorwritten permission of the publisher.IEEE Standards documents are developed within the IEee Societies and the Standards CoordinatingCommittees of the iEEE Standards Association (IEEE-SA)Standards board The ieee develops its standardsthrough a consensus development process, approved by the american National Standards Institute, which bringstogether volunteers representing varied viewpoints and interests to achieve the final product. Volunteers are notnecessarily members of the Institute and serve without compensation. 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The IEf shall not be responsible foridentifying patents for which a license may be required by an ieee standard or for conducting inquiries into thelegal validity or scope of those patents that are brought to its attentionAuthorization to photocopy portions of any individual standard for internal or personal use is granted by the Institute of Electrical and Electronics Engineers, Inc, provided that the appropriate fee is paid to Copyright ClearanceCenter. To arrange for payment of licensing fee, please contact Copyright Clearance Center, Customer Service222 Rosewood Drive, Danvers, MA01923 USA; +19787508400. Permission to photocopy portions of any indi-idual standard for educational classroom use can also be obtained through the Copyright Clearance CenterIntroductionThis introduction is not a part of IEEE Std 1364-2005, IEEE Standard for Verilog Hardware Description LanguageThe Verilog hardware description language(HDL) became an IEEE standard in 1995 as IEEE Std 13641995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in a standardtextual format for a variety of design tools, including verification simulation, timing analysis, test analysisand synthesis. It is because of these rich features that verilog has been accepted to be the language of choiceby an overwhelming number of integrated circuit(IC)designersVerilog contains a rich set of built-in primitives, including logic gates, user-definable primitives, switches,and wired logic. It also has device pin-to-pin delays and timing checks. The mixing of abstract levels isessentially provided by the semantics of two data types: nets and variables. Continuous assignments, inwhich expressions of both variables and nets can continuously drive values onto nets, provide the basicstructural construct. Procedural assignments, in which the results of calculations involving variable and netvalues can be stored into variables, provide the basic behavioral construct. a design consists of a set of modules, each of which has an input/output(1/O)interface, and a description of its function, which can be structural, behavioral, or a mix. These modules are formed into a hierarchy and are interconnected with netsThe Verilog language is extensible via the programming language interface(PLI)and the verilog procedural interface(VPi) routines. The Pli/vPi is a collection of routines that allows foreign functions to accessinformation contained in a Verilog hdl description of the design and facilitates dynamic interaction withsimulation. Applications of PLI/VPI include connecting to a Verilog HDL simulator with other simulationand computer-assisted design(CAD)systems, customized debugging TaskS, delay calculators, andannotatorsThe language that influenced Verilog HDL the most was HILO-2, which was developed at Brunel University in England under a contract to produce a test generation system for the British Ministry of DefensehiLO-2 successfully combined the gate and register transfer levels of abstraction and supported verificationsimulation, timing analysis, fault simulation, and test generationIn 1990, Cadence Design Systems placed the Verilog HDL into the public domain and the independentOpen Verilog International(oVi)was formed to manage and promote Verilog HDL. In 1992, the Board ofDirectors of ovi began an effort to establish Verilog hdl as an ieeE standard. In 1993, the first IEeEworking group was formed; and after 18 months of focused efforts, Verilog became an IEEE standard asIEEE Std 1364-1995After the standardization process was complete, the IEEe P1364 Working Group started looking for feedback from IEEE 1364 users worldwide so the standard could be enhanced and modified accordingly. Thisled to a five-year effort to get a much better Verilog standard in IEEE Std 1364-2001With the completion of IEEE Std 1364-2001, work continued in the larger Verilog community to identifyoutstanding issues with the language as well as ideas for possible enhancements. As Accellera began work-ing on standardizing System Verilog in 2001, additional issues were identified that could possibly have led toincompatibilities between Verilog 1364 and System Verilog. The IEEE P1364 Working group was established as a subcomittee of the System Verilog P1800 Working Group to help ensure consistent resolution ofsuch issues. The result of this collaborative work is this standard ieee Std 1364-2005Copyright C 2006 IEEE. All rights reservedNotice to usersErrataErrata,ifanyforthisandallotherstandardscanbeaccessedatthefollowingurL:http:/stan-dards.ieee.org/reading/ieee/updates/errata/index.html. Users are encouraged to check this URL for errataperiodicaInterpretationsCurrentinterpretationscanbeaccessedatthefollowingUrl:http:/standards.ieeeorg/reading/ieee/interp/Index. htmlPatentsAttention is called to the possibility that implementation of this standard may require use of subject mattercovered by patent rights. By publication of this standard, no position is taken with respect to the existence orvalidity of any patent rights in connection therewith. The IEee shall not be responsible for identifyingpatents or patent applications for which a license may be required to implement an IEEE standard or forconducting inquiries into the legal validity or scope of those patents that are brought to its attentionParticipantsAt the time this standard was completed, the ieee P1364 Working group had the following membershipJohny Srouji, IBM, IEEE SyStem verilog Working Group chairTom Fitzpatrick, Mentor Graphics Corporation, ChairNeil Korpusik, Sun Microsystems, Inc, Co-chairStuart sutherland sutherland hdl inc. editorShalom Bresticker, Intel Corporation, Editor through February 2005The Errata Task Force had the following membershipKaren pynopsys,rKurt baty. WFSDB ConsultinDennis marsa. XilinxStefen Boyd, Boyd TechnologyFrancoise Martinolle, Cadence Design Systems, IncShalom Bresticker, Intel CorporationMike McNamara, Verisity, LtdDennis Brophy, Mentor Graphics CorporationDon Mills, LCDM EngineeringCliff Cummings, Sunburst Design, IncAnders nordstrom, Cadence Design Systems, IncCharles dawson, Cadence Design Systems, IncKaren Pieper, Synopsys, IncTom Fitzpatrick, Mentor Graphics CorpoBrad Pierce, Synopsys, IncRonald goodstein, first shot Logic simulation andSteven Sharp Cadence Design Systems, IncAlec Stanculescu. Fintronic USA IncDesignStuart Sutherland. Sutherland HDL IncMark Hartog, Synopsys incGordon Vreugdenhil, Mentor Graphics CorporationJames Markevitch, Evergreen Technology GroupJason Woolf, Cadence design Systems, IncCopyright C 2006 IEEE. All rights reservedThe behavioral Task Force had the following membership:Steven Sharp, Cadence Design Systems, InC, ChairKurt Baty, WFSDB ConsultingJay lawrence. Cadence design Systems. IncStefen Boyd, Boyd TechnologyFrancoise Martinolle, Cadence Design Systems, IncShalom Bresticker, Intel CorporationKathryn McKinley, Cadence Design Systems, IncDennis brophy, Mentor graphics corporationMichael mcnamara. Verisity LtdCliff Cummings, Sunburst Design, IncDon Mills, LCDM EngineeringSteven Dovich, Cadence Design Systems, IncMehdi Mohtashemi, Synopsys, IncTom Fitzpatrick, Mentor Graphics CorporationKaren Pieper, Synopsys, IncRonald Goodstein, First Shot Logic Simulation andBrad Pierce, Synopsys, IncDesignDave Rich, Mentor Graphics CorporationKeith Gover, Mentor Graphics CorporationSteven Sharp, Cadence Design Systems, IncMark Hartoog, Synopsys, IncAlec Stanculescu. Fintronic USAEnnis Hawk, Jeda TechnologiesStuart Sutherland. Sutherland hdl. IncAtsushi kasuya, Jcda TechnologicsGordon Vrcugdcnhil, Mentor Graphics CorporationThe PLI Task Force had the following membershipCharles Dawson, Cadence Design Systems, Inc, ChairGhassan Khoory, Synopsys, Inc Co-chairTapati Basu, Synopsys, IncMichael rohleder. Freescale Semiconductor. IncSteven Dovich, Cadence Design Systems, IncRob Slater, Freescale Semiconductor IncRalph duncan, Mentor Graphics CorporationJohn Stickley, Mentor Graphics CorporationJim garnett, Mentor Graphics CorporationStuart Sutherland. Sutherland HDL. incJoao geada CLK Design AutomationBassam Tabbara. Novas software. IncAndrzej litwiniuk, Synopsys, IncJim Vellenga, Cadence Design Systems, IncFrancoise Martinolle, Cadence Design Systems, IncDoug Warmke, Mentor Graphics CorporationSachchidananda Patel, Synopsys, IncIn addition, the working group wishes to recognize the substantial efforts of past contributorsMichael McNamara, Cadence Design Systems, Inc1364 Working Group past chair(through September 2004)Alec Stanculescu, Fintronic USA, 1304 Working Group past vice-chair(through June 2004)Stefen Boyd, Boyd Technology, ETF past co-chair(through November 2004)The following members of the entity balloting commitlee voted on this standard. Balloters may have votedfor approval, disapproval, or abstentionAccelleraIntel CorporationBluespec, Inc.Mentor Graphics CorporationCadence Dcsign Systcms, IncSun microsystems, IncIntronic u.s.aSunburst design, IncIBMSutherland hdl lncInfineon TechnologiesSynopsys, IncCopyright C 2006 IEEE. All rights reservedWhen the IEEE-SA Standards Board approved this standard on 8 November 2005, it had the followingmembershipSteve M. mills. chairRichard h. hulett vice chairDon wright Past chairJudith gorman. secretaryMark d. bowmanWilliam B HopfT W. olsenDennis B. BrophyLowell G. JohnsonGlenn parsonsJoseph brudeHerman KochRonald c. petersenRichard coxJoseph L. Koepfinger*Gary s. RobinsonBob davisDavid J lawFrank stoneJulian forster kDaleep c mohlaMalcolm v thadenJoanna n. gueninPaul nikolichRichard l. townsendS. HalpJoe d. watseRaymond hapemanHoward L, wolfmanAlso included are the following nonvoting Ieee-Sa Standards board liaisonsSatish K. aval, NRC RepresentativeRichard Deblasio, DOE RepresentativeAlan H. Cookson, NIST RepresentativeMichelle d, trIEEE Standards Project EditoCopyright C 2006 IEEE. All rights reservedContentsOverview1. 2 Conventions used in this standard1.3SIption1 4 Use of color in this standard1.5 Contents of this standard1.6 Deprecated clauses……….….….….…1.7 Header file listings....18 Examples…………………1.9PNormative references63. Lexical conventions83.1 Lexical tokens3.2 White space3. 3 Comments中··…·········:···············中·····“:·:·:·4·····“··········3. 4 Operators3. 5 Numberssteger constants3.5.2 Real constants123.5.3 Conversion123.6 Strings123.6. 1 String variable declaration133.6.2 String manipulation133.6.3 Special cha3.7 Identifiers. keds, and syste143.7.1 Escaped identifiers143.7.2 Keywords153.7.3 System tasks and functions3.7.4 Compiler directives153.8 Attrib163.8.1 Examples3.8.2 SyIata typ··4.1 Val214.2 Nets and variables4.2.1 Net declarations4.2.2 Variable declarations4.3V4.3.1g v244.3.2 Veclor net accessibility44.4 Strengths4.4.1 Charge strength4.4.2 Drive strength.....卓········中····“·········:·····················:········254.5 Implicit declarations4.6 Net types………264.6.1 Wire and tri nets264.6.2 Wired nets4.6.3TCopyright C 2006 IEEE. All rights reserved4.6.4 Trio and tri l nets4.6.5 Unresolved nets4.6.6 Supply nets324.7 Regs324.8 Integers, reals, times, and realtime4.8.1 Operators and real numbers4.8.2 Conversion4.9 Arrays4.9.1Net arrays…·中·····:··344.9.2 reg and variable arrays344.9.3 Memories4.10 Parameters…………………354.10.1 Module parameters…364.10.2 Local parameters(localparam““374.10.3 Specify parameters……384. Name spaces…39Expressions……5.1 Operators41Operators with real operands425.1.2 Operator precedence………5.1.3 Using integer numbers in expressions…….445.1.4 Expression evaluation order……2451. 5 Arithmetic operators5.1.6 Arithmetic expressions with regs and integers5. 1.7 Relational operators485.1.8Equ495.1.9 Logical operators…495.1.10 bitw isators505.1.11 Reduction operators5.112 Shift operators…….535. 1. 13 Conditional operator535.1. 14 Concatenations545.2 Operands………5.2. 1 Vector bit-Select and part-select addressing..565.2.2 Array and memory addressing.......,.……5.2.3ings585.3 Minimum, typical, and maximum delay expressions5.4 Expression bit lengths5.4.1 Rules for expression bit lengths65.4.2 Examole of expression bit-length problerpl635.4.3 Example of self-determined expressions.645.5 Signed expressions5.5.1 Rules for expression types.....5.5.2 Steps for evaluating5.5.3 Steps for evaluating an assignment5.54 Handling X and Z in signed expressions………5.6 Assignments and truncation6. Assignments……………686.1 Continuous assignments686. 1. 1 The net declaration assignment6.1.2 The continuous assignment statement·····中···:·:·4·中·····6.1.371Copyright C 2006 IEEE. All rights reserved
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动态贝叶斯网络
动态贝叶斯网络（Dynamic Bayesian Network, DBN），是一个随着毗邻时间步骤把不同变量联系起来的贝叶斯网络。这通常被叫做“两个时间片”的贝叶斯网络，因为DBN在任意时间点T，变量的值可以从内在的回归量和直接先验值（time T-1）计算。DBN是BN（Baysian Network）的扩展，BN也称作概率网络（Probabilistic Network）或信念网络（Belief Network）。前言不确定性理论在人工智能机器学习、自动控制领域已经得到越来越广泛的应用。本书以当前国际上不确定性研究领域的核心工具—动态贝叶斯网络为线索,进行了动态网络推理算法、平稳系统动态贝叶斯网络结构学习模型设计、非平稳系统动态网络变结构学习模型设计、基于概率模型进化算法的动态贝叶斯网络结构寻优算法的研究。推理算法以隐变量作为划分依据,讨论了离散、连续、混合模型的推理算法,并进行了算法复杂度及应用领域的讨论;结构学习研究首先从度量体制人手,讨论了动态网络度量体制的可分解性,提出了平稳及非平稳系统网络结构学习模型,以及基于贪婪算法思想的遗传算法寻优思想;最终将推理及结构学习理论用于无人机路径规划、战场态势感知、动态数据挖掘、自主控制领域,并通过大量仿真检验。本书的研究工作得到了西安工业大学专着甚金及国家自然科学基金重大研究计划(90205019)的资助。本书全面系统地介绍了动态贝叶斯网络的相关理论,重点介绍了动态网络的经典应用和国内外的新发展。全书共分9章。第1章概述了动态贝叶斯网络的产生与发展、基本操作及表达。第2章和第3章为本书的理论基础部分,首先从静态网络已经取得的理论成果及研究内容人手,由浅入深引出动态贝叶斯网络的基本概念及研究方向,确定本书将要解决的主要问题:DBN推理问题和连续变量的DBN结构学习问题。第4章在第3章基础上,详细讨论了三类动态贝叶斯网络的推理即隐变量离散、隐变量连续、隐变量混合DBN推理;隐马尔科夫模型是所有离散动态网络的基础,故首先介绍其表达及推理,由此派生出其他离散动态网络,并讨论了奶何将复杂离散网络转化为简单HMM的方法,通过算法复杂度实验分析,明确了离散动态网络的相应属性,得出了相应结论,为合理选择DBN推理算法提供依据;在推理中,若系统参数未知或为时变系统,必然涉及参数学习,故在讨论三类网络的推理中亦涉及参数学习问题。第5章从静态网络结构度量机制入手,讨论并推导出动态贝叶斯网络结构用于网络结构度量的BIC及BD度量机制;通过描述基于概率模型进化算法的构图基础,引出动态贝叶斯网络结构学习机制,即基于贝叶斯优化(BOA)的动态网络结构寻优算法,BOA算法的关键是根据优良解集学习得到动态贝叶斯网络,以及根据动态贝叶斯网络推理生成新个体,前者更为重要,按照本书提出的基于贪婪箅法思想的遗传算法解决动态网络学习,然后应用动态贝叶斯网络前向模拟完成后一步。第6章在此基础上,刻画了基于BD度量体制的平稳动态系统DBN结构学习模型设计,并通过仿真验证了其有效性针对非平稳随机系统DBN的结构学习模型,提出了一种自适应窗口法用于在线自适应学习变结构DBN结构,仿真结果可行。第7章在第4章DBN推理理论的基础上,从以往UCAⅴ路径规划中使用的方法以及涉及的定义、术语等出发,讨论了静态路径规划、动态路进规划及空间路径规划三方面的基本问题,通过对原始 Voronoi图的改进,提出了平面改进型Voronoi图、空间改进型 Voronoi图的概念,以及平面及空间动态路径重规划区域原则等,为动态路径规划提供有力的整体构型支撑,进而应用前几章理论基础,建立基于DBN的战场环境感知模型,仿真结果均表明了构图及动态决策模型的正确性。第8章在DBN推理及结构学习的理论基础上,将其用于自主优化及动态数据挖掘。将BOA及基于概率模型的遗传算法的静态图形的优化机制进行推广,提出了一种动态优化的新方法,利用DBN作为t到t+1代转移网络,适时改变优化的基本条件,实时确立新的种群及优化的方向,使得自主智能体在无人干预下顺利完成一系列复杂任务成为可能,将变结构DBN结构学习模型设计用于动态数据挖掘,实时确定个因素之间的关系。第9章通过两个典型的应Ⅳ用实例,将DN推理学习理论进行融合,并用于实际模型。附录给出了与DN结构度量相关定理、性质的证明,为读者进一步研究和学习动态贝叶斯网络提供参考。本书是作者近年来潜心学习和研究国内外不确定性算法理论、方法和应用成果的一个总结。在本书的编写过程中,得到了西安电子科技大学焦李成教授和清华大学戴琼海教授及英国BankUniversity陈大庆教授的热心指导和鼓励,新加坡南洋理工大学的王海芸博土后审阅了书稿,并提出了许多宝贵意见,特向他们表示衷心的感谢。由于涉及内容广泛及限于作者的学识水平,书中疏漏和不当之处在所难免,希望读者不吝赐教指正。作者目录第1章图模型与贝叶斯网络1.1图模型简介1.2动态贝叶斯网络鲁+垂香曲1.3动态贝叶斯网络应用研究1.3.1动态时序数据分析与挖掘曾··會世57781.3.2无人机的态势感知与路径规划1.3.3.进化算法与动态贝叶斯网络混合优化…10第2章静态贝叶斯网络…112.1静态贝叶斯置信网络2.2贝叶斯网络的特点与应用范围……………152.3贝叶斯网络的研究内容162.3.1计算复杂性162.3.2网络结构的确定问题2.3.3已知结构的参数确定问题…………182.3.4在给定结构上的概率计算…4福通而看高自曲着看西画192.3.5贝叶斯网络推理算法…………………19第3章动态贝叶斯网络基础283.1从静态网到动态网283.1.1概述283.1.2推导…………………………293.1.3动态贝叶斯网络表达要鲁垂鲁鲁中t曲·曹市壘曾曹吾普·量313.2动态贝叶斯网络的研究内容…………353.2.1动态贝叶斯网络推理……………………363.2.2动态贝叶斯网络学习…………………………39第4章动态贝叶斯网络推理464.1隐变量离散动态网络推理464.1.1模型数学描述…………………464.1.2马尔科夫的研究内容…4.1.3隐马尔科夫推理学习仿真…534.1.4隐马尔科夫其他拓扑形式…………564.1.5一般离散动态网络和隐马尔科夫关系584.2动态贝叶斯网络推理算法性能分析604.2.1动态网络转化隐马尔科夫仿真…614.2.2离散动态网络推理算法比较仿真……634.2.3连续动态网络推理比较仿真………724.3模糊推理与隐马尔科夫结合炮火校射……………754.3.1概述…音曲曹香音音音吾晋自粤吾·自·754.3.2模糊动态网络环境感知框架754.4隐变量连续动态网络推理4.4.1模型数学描述…794.4.2卡尔曼滤波图模型推理·日·曹曹曾鲁····804.5混合隐状态动态贝叶斯网络834.5.1模型数学描述……b音量章申曾要中命要即命·甲看834.5.2混合动态贝叶斯网络推理864.5.3混合动态贝叶斯网络学习89第5章动态贝叶斯网络结构学习算法……915.1动态贝叶斯网络结构度量体制…………915.1.1概述…………915.1.2动态网络的贝叶斯信息度量935.1.3动态贝叶斯网络BD度量965.2动态贝叶斯网络度量分解性能分析省着带鲁曹曹曹鲁鲁鲁虚鲁鲁中·985.3构建动态网络结构寻优算法…1145.3.1基于概率模型的进化算法…1155.3.2基于贝叶斯优化构造动态网络结构算法…1165.3.3学习动态贝叶斯网络……………1185.3.4动态夏叶斯网络推理1275.4基于贝叶斯优化构建动态网络结构算法仿真…128第6章动态贝叶斯网络结构学习模型1346.1平稳系统动态网络结构学习模型设计1346.1.1模型设计1356.1.2仿真试验1386.2变结构动态网络自适应结构学习模型设计…………1446,2,1模糊自适应双尺度1446.2.2动态系统非平稳程度和平稳性的测量1516.3非平稳系统网络结构学习仿真试验153第7章基于动态贝叶斯网络的路径规划1657.1无人机平面静态路径规划…1657.1.1基本概念……………1657.1.2基于相同威胁体的路径规划…1667.1.3不同威胁体下平面路径规划1717.1.4路径细化暨要命要曹吾帝吾辛事壶要面要吾吾曹中垂要晋吾曹事1767.2无人机动态路径规划1787,2.1概述1797.2.2平面动态环境下局部路径构图原则1797.2.3威胁变化下无人机平面路径规划………1827.2.4突发威胁体下无人机平面路径重规划研究1867.3无人机空间路径规划研究………………………1907.3.1空间改进型 Voronoi图………1907.3.2威胁变化下局部路径构图区域原则1957.3.3局部路径选择原则及战场感知模型…197第8章基于动态贝叶斯网络的自主控制…1998.1概述…1998.2快速构建决策网络结构方法…2008.2.1链形决策网络模型的建立………2018.2.2决策网络树形模型结构学习算法…2048.2.3一般决策网络结构学习算法2058.3进化算法与动态网络混合优化……2068.3.1算法基本思想2068.3.2转移网络作用中鲁鲁··章鲁···自··………2108.3.3混合优化自主控制算法描述…2108.3.4混合优化自主控制算法软件实现………211第9章无人机自主控制应用研究2249.1基于混合优化的无人机路径重规划.2249.1.1自主控制过程描述2249.1.2混合优化无人机路径规划仿真…2259.2无人机攻击多目标路径规划………………2379.2.1自主控制过程描述……………2389.2.2初始动态网络图构型2399.2.3无人机自主攻击多随机运动目标仿真240附录贝叶斯网络局部结构度量数学基础250A.1链形模型局部结构度量250A.2树形模型局部结构度量253A.3局部贝叶斯网络度量………………………………257参考文献…………………………………262
- 2021-05-06下载
- 积分：1
