5G Mobile and Wireless Communications Technology
关于5G通信和无线传输的相关知识5G Mobile and wirelessCommunications TechnologyEDITED BYAFIF OSSEIRANEricssonJOSE F MONSERRATUniversitat politecnica de valenciaPATRICK MARSCHCAMBRIDGEUNIVERSITY PRESSCAMBRIDGEUNIVERSITY PRESSUniversity Printing House, Cambridge CB2 8BS, United KingdomCambridge University Press is part of the University of CambridgeIt furthers the Universitys mission by disseminating knowledge in the pursuit ofeducation learning and research at the highest international levels of excellencewww.cambridge.orgInformationonthistitlewww.cambridge.org/9781107130098C Cambridge University Press 2016This publication is in copyright. Subject to statutory exceptionand to the provisions of relevant collective licensing agreementsno reproduction of any part may take place without the writtenpermission of Cambridge University PressFirst published 2016Printed in the United Kingdom by TJ International Ltd. Padstow Cornwalla catalogue record for this publication is available from the british libraryLibrary of Congress Cataloguing in Publication dataOsseiran. Afif editor5G mobile and wireless communications technology /[edited by] Afif Osseiran, EricssonJose F monserrat, Polytechnic University of Valencia, Patrick Marsch, Nokia NetworksNew York: Cambridge University Press, 2016LCCN2015045732|ISBN978110713009( hardback)LCSH: Global system for mobile communications. Mobile communication systems- StandardsLCC TK5103483A152016DDC62138456dc23Lcrecordavailableathttp://icCn.loc.gov/2015045732IsBN 978-1-107-13009-8 HardbackCambridge University Press has no responsibility for the persistence or accuracy ofURLS for external or third- party internet websites referred to in this publicationand does not guarantee that any content on such websites is, or will remainaccurate or appropriateTo my new born son S, my twin sons H& N, my wife L s-y for her unwaveringencouragement, and in the memory of a great lady my aunt K eA OsseiranTo my son, the proud fifth generation of the name Jose Monserrat. And with thewarmest love to my daughter and wife, for being always there.E MonserratTo my two small sons for their continuous energetic entertainment, and my dearwife for her amazing patience and support.P MarschContentsList of contributorspage xIvForewordAcknowledgmentsXIXAcronymsXXIIIntroduction1. 1 Historical background1.1.1 Industrial and technological revolution: from steam enginesto the internet1. 1.2 Mobile communications generations: from IG to 4G1.1.3 From mobile broadband ( mbb) to extreme MBB1. 1.4 IoT: relation to 5G1.2 From ICT to the whole economy6771.3 Rationale of 5G: high data volume, twenty-five billion connecteddevices and wide requirements1.3.1 Security1.4 Global initiatives1. 4.1 METIS and the 5G-PPP1. 4.2 China: 5G promotion group2241. 4.3 Korea: 5G Forum141. 4.4 Japan: ARIB 2020 and Beyond Ad Hoc1. 4.5 Other 5G initiatives14.6 Iot activities1.5 Standardization activities445551.5.1ITU-R1.5.23GPP161.5.3 EEE161.6 Scope of the book16References185G use cases and system concept212. 1 Use cases and requirements212.1.1 Use cases212. 1.2 Requirements and key performance indicatorsContents2.2 5G system concept322.2.1 Concept overview322. 2.2 Extreme mobile broadband342.2.3 Massive machine-type communication362.2.4 Ultra-reliable machine-type communication382.2.5 Dynamic radio access network392.2.6 Lean system control plane432. 2. 7 Localized contents and traffic flows52.2.8 Spectrum toolbox2. 3 Conclusions48References48The 5g architecture503.1 Introduction503.1.1 NFV and SDN503.1.2 Basics about ran architecture533.2 High-level requirements for the 5G architecture563.3 Functional architecture and 5g flexibility573.3.1 Functional split criteria583.3.2 Functional split alternatives593.3.3 Functional optimization for specific applications3.3.4 Integration of lte and new air interface to fulfill 5Grequirements3.3.5 Enhanced Multi-RAT coordination features663. 4 Physical architecture and 5G deployment3.4.1 Deployment enablers673.4.2 Flexible function placement in 5G deployments713.5 Conclusions74References75Machine-type communications774.1 Introduction774.1.1 Use cases and categorization of mto774.1.2 MTC requirements804.2 Fundamental techniques for MTC834.2.1 Data and control for short packets834.2.2 Non-orthogonal access protocols854.3 Massive mtc864.3.1 Design principles864.3.2 Technology components864.3. 3 Summary of mMTC features944.4 Ultra-reliable low-latency MTC944.4. 1 Design principles944.4.2 Technology componentsContents4.4.3 Summary of uMTC features1014.5 Conclusions102References103Device-to-device(D2D)communications1075.1 D2D: from 4G to 5G1075.1.1 D2D standardization: 4G LTE D2D1095.1. 2 D2D in 5G: research challenges1125.2 Radio resource management for mobile broadband D2D1135.2.1 RRM techniques for mobile broadband d2d5.2.2 RRM and system design for D2D1145.2.3 5G D2D RRM concept: an example5.3 Multi-hop d2d communications for proximity and emergencyservices1205.3.1 National security and public safety requirements in 3GPPand Metis1215.3.2 Device discovery without and with network assistance125.3.3 Network-assisted multi-hop d2d communications1225.3.4 Radio resource management for multi-hop D2D1245.3.5 Performance of D2D communications in the proximitcommunications scenario1255. 4 Multi-operator d2d communication1275.4.1 Multi-operator D2D discovery275.4.2 Mode selection for multi-operator D2D1285.4.3 Spectrum allocation for multi-operator D2D295.5 Conclusions133References1346Millimeter wave communications1376. 1 Spectrum and regulations1376.2 Channel propagation1396.3 Hardware technologies for mm W systems1396.3.1 Device technology1396.3.2 Antennas1426.3.3 Beamforming architecture1436.4 Deployment scenarios6. 5 Architecture and mobility1466.5.1 Dual connectivit1476.5.2 Mobility1476.6 Beamforming1496.6. 1 Beamforming techniques1496.6.2 Beam finding1506.7 Physical layer techniques1526.7.1 Duplex scheme152
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MIPI Alliance Specification for D-PHY
MIPI Alliance Specification for D-PHY Version 1.00.00 – 14 May 2009配合“MIPI Alliance Specification for Camera Serial Interface 2 (CSI-2)“ 一起看。http://download.csdn.net/detail/micro_st/4242724Version1.00.0014-May-2009MIPI Alliance Specification for D-PHY2 The material contained herein is not a license, either expressly or impliedly, to any IPR owned or3 controlled by any of the authors or developers of this material or MIPl. The material contained herein is4 provided on an"as iS basis and to the maximum extent permitted by applicable law, this material is5 provided AS IS AND WITH ALL FAULTS, and the authors and developers of this material and MIP6 hereby disclaim all other warranties and conditions, either express, implied or statutory, including, but not7 limited to, any (ifany)inplied warranties, duties or conditions of merchantability, of fitness for a8 particular purpose, of accuracy or completeness of responses, of results, of workmanlike effort, of lack of9 viruses, and of lack of negligence10 All materials contained herein are protected by copyright laws, and may not be reproduced, republisheddistributed, transmitted, displayed, broadcast or otherwise exploited in any manner without the express12 prior written permission of MIPI Alliance. MIPl, MIPI Alliance and the dotted rainbow arch and all related3 trademarks, tradenames, and other intellectual property are the exclusive property of MIPI Alliance and14 cannot be used without its express prior written permission15 ALSO, THERE IS NO WARRANTY OF CONDITION OF TITLE, QUIET ENJOYMENT, QUIET16 POSSESSION. CORRESPONDENCE TO DESCRIPTION OR NON-INFRINGEMENT WITH17 REGARD TO THIS MATERIAL OR THE CONTENTS OF THIS DOCUMENT.IN NO EVENT WILLI8 ANY AUTHOR OR DEVELOPER OF THIS MATERIAL OR THE CONTENTS OF THIS DOCUMENT9 OR MIPI BE LIABLE TO ANY OTHER PARTY FOR THE COST OF PROCURING SUBSTITUTE20 GOODS OR SERVICES. LOST PROFITS. LOSS OF USE. LOSS OF DATA OR ANY INCIDENTAL.21 CONSEQUENTIAL, DIRECT, INDIRECT, OR SPECIAL DAMAGES WHETHER UNDER22 CONTRACT TORT WARRANTY OR OTHERWISE ARISING IN ANY WAY OUT OF THIS OR23 ANY OTHER AGREEMENT SPECIFICATION OR DOCUMENT RELATING TO THIS MATERIAL24 WHETHER OR NOT SUCH PARTY HAD ADVANCE NOTICE OF THE POSSIBILITY OF SUCH25 DAMAGES26 Without limiting the generality of this Disclaimer stated above, the user of the contents of this Document is27 further notified that MIPI: (a)does not evaluate, test or verify the accuracy, soundness or credibility of the28 contents of this Document;(b)does not monitor or enforce compliance with the contents of this Document29 and (c)does not certify, test, or in any manner investigate products or services or any claims of compliance30 with the contents of this Document. The use or implementation of the contents of this Document may31 involve or require the use of intellectual property rights ("IPR")including(but not limited to) patents32 patent applications, or copyrights owned by one or more parties, whether or not Members of MIPIMIPI33 does not make any search or investigation for IPR, nor does miPi require or request the disclosure of any34 IPR or claims of IPR as respects the contents of this document or otherwise35 Questions pertaining to this document, or the terms or conditions of its provision, should be addressed36 MIPI Alliance. Inc37 c/o IEEE-ISTO38 445 Hoes lane39 Piscataway, NJ0885440 Alin: Board SecretaryCopyright C 2007-2009 MIPl Alliance, Inc. All rights reservedMIPI Alliance Member ConfidentialVersion1.00.0014-May-2009MIPI Alliance Specification for D-PHY42 Contents43 Draft Version 1.00.00-14 May 2009441 Overview1451.2 Purpose.…..,.,.,,.,..472 Terminology…2.1 Definitions162.2 Abbreviations…172.3 Acronyms51 3 D-PHY Introduction523.1 Summary of Phy functionality533.2 Mandatory Functionality················2054 4 Architecture21554.1 Lane modules…564.2 Master and slave2254.3 High Frequency Clock Generation22584.4 Clock lane data lanes and the phy-Protocol interface.224.5 Selectable Lane Options·;····················234.6 Lane Module Types4.6.1 Unidirectional Data Lane…264.6.2 Bi-directional data lanes26634.6.3 Clock lane.274.7 Configurations….7654.7.1 Unidirectional Configurations............664.7.2Bi-Dal Half-Duplex Configurations674.7.3 Mixed Data Lane configurations32Copyright C 2007-2009 MIPl Alliance, Inc. All rights reservedMIPI Alliance Member Confidential111Ⅴ ersion1.00.0014-May-2009MIPI Alliance Specification for D-PHY695.1Transmission Data Structure,………………………∴335.1.1Data unitsa勹5.1.2 Bit order Serialization and De-Serialization33725.1.3 Encoding and decoding735.1.4 Data Buffering,33745.2 Lane States and Line levels755.3 Operating Modes: Control, High-Speed, and Escape5. 4 High-Speed Data Transmission··········;·5. 41 Burst payload data785.4.2 Start-of-Transmission795.4.3End-of-transmission805.4.4 HS Data Transmission burst.365.5 Bi-directional data Lane turnaround5.6 Escape Mode41835.6.1Remote triggers42845.6.2 Low-Power data Transmission43855.6.3 Ultra-Low Power State865.6.4 Escape Mode State Machine43875.7 High-Speed Clock Transmission885. 8 Clock lane Ultra-Low Power State50959 Global Operation Timing Parameters.……5.10 System Power States56915.11 Initialization56925.12 Calibration5.13 Global Operation Flow Diagram57945.14 Data Rate Dependent Parameters(informative)955. 14.1 Parameters Containing Only UI values965. 14.2 Parameters Containing Time and Ul values59Copyright C 2007-2009 MIPl Alliance, Inc. All rights reservedMIPI Alliance Member ConfidentialVersion1.00.0014-May-2009MIPI Alliance Specification for D-PHY5.14.3 Parameters Containing Only Time Values…………5.14.4 Parameters Containing Only Time Values That Are Not Data Rate Dependent6 Fault detection611006.1 Contention detection1016.2 Sequence Error Detection.……611026.2.1 SoT Error621036.2.2 SOT Sync Error1046.2.3 EoT Sync Error1056.2. 4 Escape Mode Entry Command error.1066.2.5 LP Transmission Sync error621076.2.6 False Control error1086.3 Protocol Watchdog Timers(informative)62l096.3.1 HS RX Timeout6.3.2HS TX Timeout………………·················+···:··:·················∴62l116.3.3Escape mode timeout62l126.3. 4 Escape Mode Silence Timeout6.3.5 Turnaround errors114 7 Interconnect and Lane Configuration.641157.1 Lane configuration1167.2 Boundary Conditions.....…647.3 Definitions………64l187.4S- parameter Specifications………….651197.5 Characterization Conditions207.6 nterconnect Specifications………1217.6.1 Differential characteristics1227. 6.2 Common-mode characteristics671237.6.3 Intra-Lane Cross-Coupling1247. 6. 4 Mode-Conversion limitsCopyright C 2007-2009 MIPl Alliance, Inc. All rights reservedMIPI Alliance Member ConfidentialVersion1.00.0014-May-2009MIPI Alliance Specification for D-PHY1257.6.5 Inter-Lane Cross-Coupling671267. 6.6 Inter-Lane static skew1277.7 Driver and receiver Characteristics1287.7.1 Differential Characteristics1297. 7.2 Common-Mode characteristics1307.7.3 Mode-Conversion Limits1317.7.4 Inter-Lane Matching132 8 Electrical Characterislics701338.1 Driver characteristics1348.1.1 High-Speed Transmitter1358.1.2 Low-Power Transmitter1368.2 Receiver Characteristic·…············…·······…8301378.2.1 High-Speed Receiver801388.2.2Low- Power receiver.................….….821398.3 Line contention detection1408.4 Input Characteristics8441 9 High-Speed Data-Clock Timing1429.1 High-Speed Clock Timing861439.2 Forward High-Speed Data Transmission Timing871449.2.1 Data-Clock Timing Specifications1459.3 Reverse High-Speed Data Transmission Timing89146 10 Regulatory Requirements91147 Annex A Logical PHY-Protocol Inter face Description(informative)92148A 1 Signal Description149A 2 High-Speed Transmit from the Master Side150A3 High-Speed receive at the slave Sidel00151A 4 High-Speed Transmit from the Slave side152A.5 High-Speed Receive at the Master SideIOICopyright C 2007-2009 MIPl Alliance, Inc. All rights reservedMIPI Alliance Member ConfidentialVersion1.00.0014-May-2009MIPI Alliance Specification for D-PHY153A6 Low-Power Data Transmission102154A7 Low-Power Data Reception.103155A 8 Turn-around156 Annex B Interconnect Design Guidelines (informative)105157B. 1 Practical distances105158B 2 RF Frequency Bands: Interference.105B3 Transmission Line design160B4 Reference Layer.106161B 5 Printed-Circuit board106162B6 Flex-foils106163B 7 Series resistance106164B 8 Connectors106165 Annex C 8b9b Line Coding for D-PHY(normative)107166C 1 Line Coding Features...·············108167C.1.1Enabled Features for the Protocol108l68C 1. 2 Enabled Features for the Phy108169C2 Coding scheme170C 2.1 8b9b Coding Properties.....108171C 2.2 Data Codes: Basic Code Set……….109C.2.3 Comma Codes: Unique Exception Codes110173C 2.4 Control Codes: Regular Exception Codes…10174C.2.5 Complete Coding Scheme………175C 3 Operation with the D-PhY…11117yload: Data and Control177C.3.2 Details for Hs transmission………112178C.3.3 Details for LP Transmissionl12179C 4 Error Signal180C5 Extended PplCopyright C 2007-2009 MIPl Alliance, Inc. All rights reservedMIPI Alliance Member ConfidentialⅤ ersion1.00.0014-May-2009MIPI Alliance Specification for D-PHYl81C.6 Complete Code Set.….….l15182Copyright C 2007-2009 MIPl Alliance, Inc. All rights reservedMIPI Alliance Member Confidentialv111Version1.00.0014-May-2009MIPI Alliance Specification for D-PHYl83Figures184 Figure 1 Universal Lane Module functions21185 Figure2 Two Data Lane PHY Configuration.…………23186 Figure 3 Option Selection Flow Graph4187 Figure 4 Universal Lane Module Architecture25188 Figure 5 Lane Symbol Macros and Symbols Legend189 Figure 6 All Possible Data Lane Types and a basic Unidirectional Clock lane190 Figure 7 Unidirectional Single Data Lane Configuration30191 Figure 8 Unidirectional Multiple Data Lane Configuration without LPDT∴.30192 Figure 9 Two Directions Using Two Independent Unidirectional PHYs without LPDT.........31193 Figure 10 Bidirectional Single Data Lane Configuration31194 Figure 1l Bi-directional Multiple Data Lane Configuration......32195 Figure 12 Mixed Type multiple data Lane Configuration32196 Figure 13 Line level34197 Figure 14 High-Speed Data Transmission in Bursts36198 Figure 15 TX and rX State Machines for High-Speed Data Transmission37Figure16 Turnaround Procedure.……39200 Figure 17 Turnaround State Machine40201 Figure 18 Trigger-Reset Command in Escape Mode202 Figure 19 Two Data Byte Low-Power Data Transmission Example203 Figure 20 Escape Mode State Machine204 Figure2 I Switching the Clock Lane between Clock Transmission and low- Power mode………….47205 Figure 22 High-Speed Clock Transmission State Machine49206 Figure 23 Clock Lane Ultra-Low Power State State Machine········+·+···+·4···207 Figure 24 Data Lane Module State Diagram57208 Figure 25 Clock Lane Module state diagram58209 Figure 26 Point-to-point InterconnectCopyright C 2007-2009 MIPl Alliance, Inc. All rights reservedMIPI Alliance Member Confidential
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