PID控制超详细教程(含软硬件上位机，很好）
PID控制超详细教程(含软硬件上位机，很好）SUNPLUS调节控制做电机速度控制月录页模拟控制模拟控制原理数字控制位置式算法增量式算法控制器参数整定凑试法临界比例法经验法采样周期的选择参数调整规则的探索自校正控制器软件说明软件说明档案构成界面子程序说明程序范例程序程序流程与说明中断子流稈与说明使用资源硬件使用资源说明实验测试响应曲线参考文献SUNPLUS调节控制做电机速度控制修订记录日期版本编写及修订者编写及修订说明初版错误校正SUNPLUS调节控制做电机速度控制模拟控制将偏差的比例()、积分()和微分()通过线性组合构成控制量用这一控制量对被控对象进行控制,这样的控制器称控制器、模拟控制原理在模拟控制系统中,控制器最常用的控制规律是控制。为了说明控制器的工作原理,先看个例子。如图—所示是一个小功率直流电机的调速原理图。给定速度与实际转速进行比较,其差值,经过控制器调整后输出电压控制信号经过功率放大后,驱动直流电动机改变其转速。+控器直流电机图小功率直流电机调速系统常规的模拟控制系统原理框图如图—所示。该系统由模拟控制器和被控对象组成。图中是给定值是系统的实际输岀值,给定值与实际输出值构成控制偏差式-)作为控制的输入,作为控制器的输出和被控对象的输入。所以模拟控制器的控制规律为式其中:控制器的比例系数搾制器的积分时间,也称积分系数控訇器的微分时间,也称微分系数比例积分被控对象微分图—模拟控制系统原理图比例部分SUNPLUS调节控制做电机速度控制比例部分的数学式表示是:在模拟控制器中,比例环节的作用是对偏差瞬闩作岀反应。偏差一旦产生控制器立即产生控制作用,使控制量向减少偏差的方冋变化。控制作用的强弱取决于比例系数,比例系数越大,控制作用越强,则过渡过程越快,控制过程的静态偏差也就越小;但是越大,也越容易产生振荡,破坏系统的稳定性。故而,比例系数选择必须恰当,才能过渡时间少,静差小而又稳定的效果。、积分部分积分部分的数学式表小是从积分部分的数学表达式可以知道,只要存在偏差,则它的控制作用就不断的增加;只有在偏差时,它的积分才能是一个常数,控制作用才是一个不会增加的常数。可见,积分部分可以消除系统的偏差积分环节的调节作用虽然会消除静态误差,但也会降低系统的响应速度,增加系统的超调量。积分常数越大,积分的积累作用越弱,这时系统在过渡时不会产生振荡;但是增大积分常数会诚慢静态误差的消除过程,消除偏差所需的时间也较长,但可以减少超调量,提髙系统的稳定性.当较小时,则积分的作用较强,这时系统过渡时间中有可能产生振荡,不过消陰偏差所需的时间较短。所以必须根据实际控制的只体要求来确定。、微分部分微分部分的数学式表示是实际的控制系统除了希望消除静态误差外,还要求加快调节过程。在偏差岀现的瞬间,或在偏差变化的瞬间,不但要对偏差量做岀立即响应(比例环节的作用),而∏要根据偏差的变化趋势预先给岀适当的纠正。为了实现这一作用,可在控制器的基础上加入微分环节,形成控制器。微分环节的作用使阻止偏差的变化。它是根据偏差的变化趋势(变化速度)进行控制。偏差变化的越快,微分控制器的输出就越大,并能在偏差值变大之前进行修正。微分作用的引入,将有助于减小超调量,克服振荡,使系统趋于穩定,特別对髙阶系统非常有利,它加快了系统的跟踪速度但微分的作用对输入信号的噪声很敏感,对那些噪声较人的系统一般不用微分,或在微分起作用之前先对输入信号进行滤波。微分部分的作用由微分时间常薮决定。越大时,则它抑制偏差变化的作用越强棫小时,则它反抗偏差变化的作用越弱。微分部分显然对系统稳定有很大的作用。适当地选择微分常数,可以使微分作用达到最优由于计算机的出现,讣算机进入了控制领或。人们将模拟控制规律引入到计算机中来。对(式—)的控制规律进行适当的变換,就可以用软件实现控制,即数字搾制。SUNPLUS调节控制做电机速度控制数字控制数字式控制算法可以分为位置式和增量式控制算法。位置式算法由于计算杋控制是一种采样控制,它只能根据样时矧的偏差计算控制量,而不能像模拟控制那样连续输岀控制量量,进行连续控制。由于这·特点(式)中的积分项和黴分项不能直接使用,必须进行离散化处理。离散化处理的方法为:以作为采样周期,作为采样序号,则离散采样时间对应着连续时间,用矩形法数值积分近似代替积分,用一阶后向差分近似代膂微分,可作如下近似变换:≈1T〔k=0,1,2.e()h(门-Tag(),()-以(k-1)7]8-1di(式上式中,为了衣示的方便,将类似于简化成等。将(式-)代入(式一),就可以得到离散的表达式为(式一)或+(式其米样序号,一,,第次釆样时刻的计算机输出值:第次采样时刻输入的偏差值第—次采样时刻输入的偏差值:积分系数,微分系数,如果采样周期足够小,则〔式—)或(式—)的近似计算可以获得足够精确的结果,离散控制过程与连续过程十分接近。(式—)或(式一)表示的控制算法式直接按(式一)所给出的控制规律定义进行计算的,所以它给出了全部控制量的大小,因此被称为全量式或位置式控制算法这种算法的缺点是:由于全量输出,所以每次输出均与过去状态有关,计算时要对进行累加,SUNPLUS调节控制做电机速度控制工作量人;并且,因为计算杋输岀的对应的是执行机构的实际位置,如果计算机岀现故障,输岀的将大幅度变化,会引起执行机构的大幅度变化,有可能因此造成严重的生产事枚,这在实生产际中是不允许的。増量式探制算法可以避免着重现象发生。增量式算法所谓增量式是指数宇控制器的输岀只是控制量的增量Δ。当执行机构需要的控制量是增量,而不是位置量的绝对数佶时,可以使用增量式控制算法进行控制。增量式控制算法可以通过(式一)推导出。由(式一)可以得到控制器的第个采样时刻的输出值为+∑+式将(式一)与(式一)相减并整理,就可以得到增量式控制算法公式为△(式其中由(式—)可以看出,如果计算机控制系统采用恒定的采样周期日确定只要使用前后三次测量的偏差值,就可以由(式—)求出控制量。增量式控制算法与位置式算法(式一)相比,计算量小的多,因此在实际中得到广泛的应用而位置式搾制算法也可以通过增量式控制算法推岀递推计算公式:△式(式—)就是目前在计算机控制中广泛应用的数字递推控制算法控制器参数整定搾制器参数整定:指决定调节器的比例系数、积分时间、微分时间和采样周期的SUNPLUS调节控制做电机速度控制具体数值。整定的实质是通过改变调节器的参数,使其特性和过程特性相匹配,以改善系统的动态和静态指标,取得最佳的控制效果。整定调节器参数的方法很多,归纳起来可分为两大类,即理论计算整定法和工程整定法。理论计算整定法有对数频率特性法和根轨迹法等;工程整定法冇凑试法、临界比例法、经验法、衰减曲线法和响应曲线法等。工程整定法特点不需要事先知道过程的数学模型,直接在过程控制系统中进行现场整定方法简单、计算简便、易于掌握凑试法按照先比例()、再积分()、最后微分()的顺序。置调节器积分时间∞,微分时间在比例系数按经验设置的初值条件下,将系统投入运行,由小到大整定比例系数求得满意的衰减度过渡过程曲线引入积分作用(此时应将上述比例系数设置为)。将由大到小进行整定若需引入微分作用时,则将按经验值或按(~)设置,并由小到人加入临界比例法在闭坯控制系统甲,将调节器置纯比例作用卜,从小到大逐渐改变调节器的比例系教,得到竿幅振荡的过渡过程。此时的比例系数称为临界比例系数相邻两个波峰间的时间间隔,称为临界振荡周期二界比例度法步骤:将调节器的积分时间置于最大(∞),微分时间置零),比例系数适当,平衡操作一段时问,把系统投入自动运行、将比例系数逐渐增大,得到等幅振荡过程,记卜临界比例系数和临界振蕩周期值根据和值,采用经验公式,计算出调节器各个参数,即、和的值。按先再最后的操作程序将调节器整定参数调到计算值上。若还不够满意,可再作进步调整。临界比例度法整定注意事项:有的过程控制系统,临界比例系数很大,使系统接近两式控制,调节阀不是全关就是全开,对工业生产不利有的过程控制系统,当调节器比例系数调到最大刻度值时,系统仍不产生等幅振荡,对此,就把最大刻度的比例度作为临界比例度进行调节器参数整定经验法用凑试汯确定参数需要经过多次反复的实验,为了减少凑试次数,提高工作效率,可以借鉴他人的经验,并根据‘定的要求,事先作少量的实验,以得到若「基准参数,然后按照经验公式用这些基准参数导出控制参数,这就是经验法。临界比例法就是一种经验法。这种方法首先将控制器选为纯比例控制器,并形成闭环,改变比例系数,使系统对阶跃输入的响应达到临界状态,这时记下比例系数、临界振荡周期为,根SUNPLUS调节控制做电机速度控制据一提供的经验公式,就可以由这两个基准参数得到不同类型控制器的参数,如表一所示。衣—临界比例法确定的模拟控制器参数控制器类型这种临界比例汯使针对模拟ˆ控制器,对于数字控制器,只要釆样周期取的较小,原则上也同样使用。在电动机的控制中,可以先采用临界比例法,然后在采用临界比例法求得结果的基础上,用凑试法进一步完善表一的控制参数,实际上是按衰减度为时得到的。通常认为的衰减度能兼顾到稳定性和快速性。如果要求更大的衰减,则必须用凑试法对参数作进一步的调整。采样周期的选择香农()采样定律:为不失真地复现信号的变化,采样频率至少应大于或等于连续信号最高频率分量的二倍。根据采样定律可以确定采样周期的上限值。实际采样周期的选择还要受到多方面因素的影响,不同的系统采样周期应根据具体情况米选择。采样周期的选择,通常按照过程特性与丨扰大小适当来选取采样周期:郾对于响应快、(如流量、压力)波动大、易受干扰的过程,应选取较短的采样周期:反之,当过程响应慢(如温度、成价)、滞后人时,可选取较长的采样周期采样周期的选取应与参数的整定进行综合考虑,采样周期应远小于过程的扰动信号的周期,在执行器的响应速度比较慢时,过小的采样周期将失去意义,因此可适当选大ˉ点;在计算机运算速度允许的条件下,采样周期短,则控制品质好;当过程的纯滞后时间较长时,一般选取采样周期为纯滞后时间的参数调整规则的探索人们通过对控制理论的认识和长期人工操作经验的总结,可知参数应依据以卜儿点来适应系统的动态过程。在偏差比较大时,为使尽快消除偏差,提高响应速度,冋时为了避免系统响应岀现超调,取大值,取零;在偏差比较小时,为继续减小偏差,并防止超调过大、产生振荡、稳定性变坏,值要减小,取小值;在偏差很小时,为消除静差,克服超调,使系统尽快稳定,值继续减小,值不变或稍取大。当偏差与偏差变化率同号时,被控量是朝偏离既定值方向变化。因此,当被控量接近定值时,反号的比列作用阻碍积分作用,避免积分超调及随之而来的振荡,有利于控制;而当被控量远未接近各定值并向定值变化时,则由于这两项反向,将会减慢控制过程。在偏差比较大时,偏差变化率与偏差异号时,值取零或负值,以加快控制的动态过程。偏差变化率的大小表明偏差变化的速率,越大,取值越小,取值越大,反之亦然。同时,要结合偏差大小来考虑
- 2020-12-06下载
- 积分：1
altera公司IP核使用手册.PDF
altera公司IP核使用手册,对于学习EDA技术的学生或工程师有用A吉RAContentsChapter 1. About this MegaCore FunctionRelease informat1-1Device Family Support···Introduction.··········FeaturesOpen core plus evaluation1-3Performance···Chapter 2. Getting StartedDesign Flow衡·鲁·,看·,音番2-1Megacore Function walkthrough2-2Create a New quartus II Pi2-2Launch the mega Wizard Plug-in ManagerStep 1: Parameterize2-5Step 2: Set Up SimulationStep 3: Generate..,2-11Simulate the design2-13Compile the design2-13Pa Device2-14Set Up Licensing2-15ppend the license to yourdat file2-15Specify the License File in the Quartus II Software...2-15Example Simulation and Compilation..2-16Example quartus Ii project2-16Example simulation with Test Vectors,,,,,,2-16Chapter 3. SpecificationsyperTransport Technology Overview1HT SyStems3-2HT Flow ControlHyper Transport MegaCore Function SpecificationPhysical InterfaceSynchronization and alignment ...Protocol interfClocking Options.......HyperTransport Mega Core Function Parameters and HT Link Performance3-10Signals3-14CSR Module...3-31OpenCore plus time-Out BehaviorAppendix A. ParametersIntroduction鲁鲁鲁A-1Parameter listsDevice Family and Read Only registers···········,,,,,,,,,,A-1Base Address Registers番鲁,A-2Clocking OptionsA-3Advanced settingso March 2009 Altera corporationHyperTransport MegaCore Function User GuideAppendix B. Stratix Device Pin AssignmentsIntroductionB-1GuidelinesAppendix C. Example designGeneral descriptionAdditional informationRevision historyInto-lHow to Contact alteraInfo-1Typographic Conventions ..........Info-2Hyper Transport MegaCore Function User Guideo March 2009 Altera CorporationA吉RA1. About this MegaCore FunctionRelease InformationTable 1-1 provides information about this release of the Hyper Transport Mega CoretfunctioTable 1-1. Hyper Transport Mega Core Function Release InformationitenlDescription∨ ersion9.0Release dateMarch 2009Ordering codeIP-HTProduct ID(s)0098Vendor iD(s)6AF7Altera verifies that the current version of the quartus@ll software compiles theprevious version of each MegaCore function. Any exceptions to this verification arereported in the Mega Core lP Library release Notes and Errata. Altera does not verifycompilation with Mega Core function versions older than one releaseDevice Family SupportMegaCore functions provide either full or preliminary support for target Alteradevice families:Full support means the Mega Core function meets all functional and timingrequirements for the device family and may be used in production designsa Preliminary support means the Mega Core function meets all functionalrequirements, but may still be undergoing timing analysis for the device family;itmay be used in production designs with cautionTable 1-2 shows the level of support offered by the Hyper Transport MegaCorefunction for each of the altera device familiesTable 1-2. Device Family SupportDevice FamilySupportHard Copy Stratix@FullStratixFulStratix IIFulStratix‖GXPreliminaryStratix GXOther device familiesNo supportC March 2009 Altera CorporationHyperT ransport Mega Core Function User Guide1-2Chapter 1: About this MegaCore FunctionIntroductionIntroductionThe Hyper Transport Mega Core function implements high-speed packet transfersbetween physical(PhY) and link-layer devices, and is fully compliant with theHyperTransport l/O Link Specification, Revision 1.03. This Mega Core function allowsdesigners to interface to a wide range of Hyper TransportTm technology(hT)enableddevices quickly and easily, including network processors, coprocessors, videochipsets, and ASICsFeaturesThe Hyper Transport Mega Core function has the following features8-bit fully integrated hT end-chain interfacePacket-based protocolDual unidirectional point-to-point linksUp to 16 Gigabits per second(Gbps)throughput(8 Gbps in each direction)200, 300, and 400 MHz DDR links in Stratix and Stratix GX devices200, 300, 400, and 500 MHz ddr links in Stratix II and Stratix II GX devicesLow-swing differential signaling with 100-Q2 differential impedanceHardware verified with Hyper fransport interfaces on multiple industry standardprocessor and bridge devicesFully parameterized mega core function allows flexible, easy configurationFully optimized for the altera stratix Il, Stratix, Stratix GX, and Stratix II GXevice famillesApplication-side interface uses the Altera AtlanticTM interface standardManages Hr flow control, optimizing performance and ease of useIndependent buffering for each HT virtual channelAutomatic handling of ht ordering rulesStalling of one virtual channel does not delay other virtual channels(subject toorderingFlexible parameterized buffer sizes, allowing customization depending onsystem requirementsUser interface has independent interfaces for the HT virtual channels, allowingindependent user logic designCyclic redundancy code(crc) generation and checking to preserve data integrityIntegrated detection and response to common HT error conditions■ CRC errorsEnd-chain errorsFully integrated HT configuration space includes all required configuration spaceregisters and HT capabilities list registersHyper Transport MegaCore Function User Guideo March 2009 Altera CorporationChapter 1: About this MegaCore FunctionPerformance32-bit and 64-bit support across all base address registers bars)automatically handles all csr space accessesVerilog HDL and VHdL simulation supportOpen Core Plus EvaluationWith the Altera free Open Core Plus evaluation feature, you can perform the followingSimulate the behavior of a mcgafunction(Altera MegaCore function or AMPPmegafunction) within your systema Verify the functionality of your design, as well as quickly and easily evaluate itssize and speedGenerate time-limited device programming files for designs that includeMegaCore functionsProgram a device and verify your design in hardwareYou only need to purchase a license for the Mega Core function when you arecompletely satisfied with its functionality and performance and want to take yourdesign to productiono For more information about Open Core Plus hardware evaluation using theHyperTransport MegaCore function, refer to"Open Core Plus Time-Out Behavior"onpage 3-40 and AN 320: Open Core Plus Evaluation of megafunctionsPerformanceThe Hyper Transport Mega Core function uses 20 differential I/O pin pairs and 2single-ended I/O pins, requiring 42 pins total. Table 1-3 through Table 1-5 showtypical performance and adaptive look-up table (alut) or logic element (LE)usagefor the HyperTransport MegaCore function in Stratix II GX, Stratix IL, Stratix, andStratix GX devices respectively, using the Quartus@ II software version 7.1Table 1-3 shows the maximum supported data rates in megabits per second(Mbps)by device family and speed gradeTable 1-3. Maximum Supported Hyper Transport Data Rates (Note 1)Speed GradeDevice Family-36Stratix ll GX devices 1000 Mbps 1000 Mbps 800 MbpsNA(2)N/A(2NA(2)Stratix devices1000 Mbps 1000 Mbps 800 Mbps N/A(2)NA(2)NA(2)Stratix devicesN/A(2N/A(2)00 Mbps 800 Mbps 600 Mbps400 MbpsFlip-Chip packagesStratix devicesNA(2)NA(2)NA(2)600 Mbps400 Mbps400 Mbps(Wire Bond packagesStratix GX devicesN/A(2) N/A(2)800 Mbps 800 Mbps 600 Mbps N/A(2)Notes to table 1-3(1)Rates are per interface bit. Multiply by eight to calculate the uni-directional data rate of an 8-bit inter face(2) Devices ot this speed grade are not ottered in this device familyC March 2009 Altera CorporationHyperTransport Mega Core Function User GuideChapter 1: About this MegaCore FunctionPerformanceTable 1-4 shows performance and device utilization for the Hyper TransportMegaCore function in Stratix II and Stratix II GX devicesTable 1-4. Hyper Transport Mega Core Function Performance in Stratix ll and Stratix ll GX DevicesParametersMemoryUserRXCombinationalHT Link InterfacePosted Non-Posted Response ClockingALUTSLogicfMAX(MHz) MAx(MHz)Buffers BuffersBuffers Option(12)Registers M4K M512 ( 3)3)Shared3.5005200120500125(4RX/TX/Ref35005200500Ref/x8Shared36005400160500>150RX/TXShared4.0006,00016150RX/TX16Shared4,1006,200500125(4)RX/TX/RefShared4.1006200500125(4Ref/TxShared4.2006400160150RX/TXNotes to table 1-4.Refer to " Clocking Options "on page 3-7 for more information about these options(2 )Other parameters(BAR configurations, etc. )vary the alut and Logic Register utilization numbers by approximately +/-200(3)Figures for -3 speed grade devices only(4) When using the Shared Rx/Tx/Ref and Shared Ref/Tx options, the user interface frequency is limited to exactly the ht frequency divided byTable 1-5 shows performance and device utilization for the Hyper TransportMegaCore function in Stratix and Stratix GX devicesTable 1-5. Hyper Transport Mega Core Function Performance in Stratix and Stratix GX DevicesUser Interface fmaxParametersUtilizationHT Link fMAX MHz)MHZ)RXRXSpeed GradePosted Non-Posted Response Clocking Option LEsM4KBuffers BuffersBuffers)(2 Blocks.5-66Shared rx/tx/ref1240010073)100734448888Shared Ref/Tx 7, 60014400400100{3)100(3)Shared rxtx7,90016400400>125>100Shared rxtx8.900125>100168Shared Rx/T×Ref9,400124004001003)100316Shared ref/ ix9.500144001003)10073)16Shared rx/x9.700400125Notes to table 1-5:(1)Refer to Clocking Options"on page 3-7 for more information about these options(2 )Other parameters( BAR configurations etc. )vary the LE utilization by approximately +/-200 LES(3 )When using the Shared Rx/Tx/ Ref and Shared Ref/Tx options, the user interface frequency is limited to exactly the hT frequency divided by fourHyper Transport MegaCore Function User GuideC March 2009 Altera CorporationA吉RA2. Getting StartedDesign FlowTo evaluate the HyperTransport Mega Core function using the Open Core Plus feature,include these steps in your design flowObtain and install the HyperTransport Mega Core functionThe HyperTransport Mega Core function is part of the MegaCore IP Library, which isdistributed with the Quartus ii software and downloadable from the altera websitewww.altera.como For system requirements and installation instructions, refer to Quartus II InstallationLicensing for Windows and Linux Workstations on the Altera website atwww.altera.com/literature/lit-qts.ispFigure 2-1 shows the directory structure after you install the HyperTransportMegaCore function, where is the installation directory. The default installationWindows is C: altera ; on Linux it islopt/alteraFigure 2-1. Directory StructureInstallation directorypContains the Altera MegaCore IP Library and third-party IP coresalteraContains the Altera MegaCore IP LibrarycommonContains shared componentshtContains the Hyper Transport Hyper Transport Megacore function files and documentationdocContains the documentation for the Hyper Transport MegaCore functionlibContains encrypted lower-level design filesexampleContains the design example for the Hyper Transport Mega Core function2. Create a custom variation of the Hyper Transport Mega Core function3. Implement the rest of your design using the design entry method of your choice4. Use the IP functional simulation model to verify the operation of your designo For more information about Ip functional simulation models, refer to the SimulatingAltera IP in Third-Party Simulation Tools chapter in volume 3 of the Quartus II Handbook5. Use the Quartus II software to compile your designC March 2009 Altera CorporationHyperT ransport Mega Core Function User Guide2-2Chapter 2: Getting StartedMega Core Function WalkthroughIg You can also generate an Open Core Plus time-limited programming file,which you can use to verify the operation of your design in hardware6. Purchase a license for the hypertransport Mega Core functionAfter you have purchased a license for the Hyper transport mega Core functionfollow these additional steps1. Set up licensing2. Generate a programming file for the Altera device(s)on your board3. Program the Altera device(s)with the completed designMegaCore Function WalkthroughThis walkthrough explains how to create a custom variation using the AlteraHyper Transport IP Toolbench and the Quartus II software, and simulate the functionusing an ip functional simulation model and the modelsim software when you arefinished generating your custom variation of the function, you can incorporate it intoⅴ our overall projectIe IP Toolbench allows you to select only legal combinations of parameters, and warnsou of any invalid configurationsIn this walkthrough you follow these stepsCreate a New Quartus II Projecta Launch the MegaWizard Plug-in Manager■Step1: Parameterizea Step 2: Set Up Simulation■Step3: Generate■ Simulate the designTo generate a wrapper file and Ip functional simulation model using default values,omit the procedure described in"Step 1: Parameterizeon page 2-5Create a New Quartus ll ProjectCreate a new Quartus II project with the New Project Wizard, which specifies theworking directory for the project, assigns the project name, and designates the nameof the top-level design entityTo create a new project, perform the following steps1. On the Windows Start menu, select Programs> Altera> Quartus II tostart the Quartus lI software. Alternatively, you can use the Quartus II Web editionsoftware2. In the Quartus II window, on the File menu, click New Project Wizard. If you didnot turn it off previously, the New Project Wizard Introduction page appears3. On the New Project Wizard Introduction page, click NextHyper Transport MegaCore Function User Guideo March 2009 Altera Corporation
- 2020-12-05下载
- 积分：1
