万有引力搜索算法

采用Multisim进行的仿真，内部含万用表内的各种检测分电路和总体（包括直流/交流的电流/电压 以及欧姆表），是自己本科时候的课程设计时候制作的，内容比较详细，仿真电路是全的，具体要求和详细分析找不到了，应该有一定的参考价值。

基于bp神经网络的变压器故障检测，模型训练及模型测试。

本设计是利用 VHDL 硬件描述语言设计 CRC 发生器和校验器 。12 位信息加 5 位 CRC 校验码发送 、 接收 ,由两个模块组成 ,CRC 校验生成模块 ( 发送) 和 CRC校验检错模块 ( 接收) ,采用输入,输出都为并行的 CRC校验 生 成 方 式 。产 生 此 CRC 码 可 利 用 Peterson 和Brown 提出的移位寄存器电路实现 。初始时置各寄存器为 0 ,信息位串从高位起逐位输入电路 ,每送入一位就进行一次异或操作和循环移位 ,由于信息位串为 12 位 ,所以经过 12 次操作后 ,4 个寄存器中的值就是冗余位 。

多目标粒子群的论文和代码。绝对的经典。目前就找到这么一个程序，能够很好地运行，没有错误。而且对照着原论文看很容易看明白。希望给需要的人以帮助，大家一起进步

multisim 11的TL494模型仿真

【实例简介】可以运行的3相全控桥PWM波形产生电路matlab仿真建模

目标识别是计算机视觉一个重要的研究领域，由此延伸出的车辆型号识别具有重要的实际应用价值，特别是在当今交通状况复杂的大城市，智能交通系统成为发展趋势，这离不开对车辆型号进行识别和分类的工作，本文围绕如何利用计算机视觉的方法进行车辆型号的识别和分类展开了一系列研究：本文对当前的目标识别和分类的特征和算法做了总结和归纳。分析比较了作为图像特征描述常见的特征算子，总结归纳了他们的提取方法、特征性能以及相互之间的关联。另外，介绍了在目标识别工作中常用的分类方法,阐述了他们各自的原理和工作方法。研究了深度神经网络的理论依据，分析比较了深度神经网络不同的特征学习方法，以及卷积

基于51单片机的DS18B20温度控制器源程序代码。

Hilbert-Huang希尔伯特黄变换(HHT)的Matlab实现，亲自验证代码可用，最全版本

The Verilog® Hardware Description Language (Verilog HDL) became an IEEE standard in 1995 as IEEEStd 1364-1995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in astandard textual format for a variety of design tools, including verification simulation, timiThe clear directive from the users for these three task forces was to start by solving some of the followingproblemsConsolidate existing IeeE Std 1364-1995Verilog generate statementMulti-dimensional arraysEnhanced Verilog file i/oRe-entrant tasksStandardize Verilog configurationsEnhance timing representationEnhance the vpi routinesAchievementsOver a period of four years the 1364 Verilog Standards Group(vsg) has produced five drafts of the lrmThe three task forces went through the EEe Std 1364-1995 lRM very thoroughly and in the process of consolidating the existing Lrm have been able to provide nearly three hundred clarifications and errata for theBehavioral, ASIC, and PLI sections. In addition, the vsg has also been able to agree on all the enhance-ments that were requested (including the ones stated above)Three new sections have been added. Clause 13, "Configuring the contents of a design, deals with configuration management and has been added to facilitate both the sharing of verilog designs between designersand/or design groups and the repeatability of the exact contents of a given simulation session Clause 15Timing checks, "has been broken out of Clause 17, "System tasks and functions, "and details more fullhow timing checks are used in specify blocks. Clause 16, "Backannotation using the Standard Delay Format(SDF), addresses using back annotation(IEEE Std 1497-1999)within IEEE Std 1364-2001Extreme care has been taken to enhance the vpi routines to handle all the enhancements in the behavioraland other areas of the lrm. minimum work has been done on the pli routines and most of the work hasbeen concentrated on the vpi routines. Some of the enhancements in the vpi are the save and restart simu-lation control, work area access, error handling, assign/deassign and support for array of instances, generateand file 1/0Work on this standard would not have been possible without funding from the cas society of the ieee andOpen verilog InternationalThe IEEE Std 1364-2001 Verilog standards Group organizationMany individuals from many different organizations participated directly or indirectly in the standardizationprocess. The main body of the Ieee Std 1364-2001 working group is located in the United States, with asubgroup in Japan (EIAJ/1364HDL)The members of the IEEE Std 1364-2001 working group had voting privileges and all motions had to beapproved by this group to be implemented the three task forces focused on their specific areas and theirrecommendations were eventually voted on by the Ieee Std 1364-2001 working group