非常好用的融合图像评价方法

华为内部文档——眼图指标介绍，详细分析了眼图的一些指标和问题的分析，适用于光纤通信方面的设计-Huawei internal document - the eye diagram of indicators, the detailed analysis of the eye diagram of a number of indicators and analysis, applied to optical fiber communication design

【实例简介】《PyQt5快速开发与实战》 是学习使用PyQt5构建windows界面的经典书籍，这是它的随书源码。

清华大学智能控制概论课件ppt,非常好。珍惜！

Criminisi算法可对彩色图像进行修复，matlab代码，包含测试图像和实例代码，可运行

该程序主要是在STM32F407平台下，外加一个LAN8742A的PHY模块，加载LwIP及FreeRTOS，本例使用CubeMX软件生成原始工程，并在该工程基础之上进行相应的线程添加，并调试完成，成功实现ping,TCP回响测试功能，达到预期的目的。

设计一个基于开发板的通信系统，要求在给定的开发板DE10-Lite上，完成以下任务：1） 完成数模转换、四进制调制解调（fsk）；2） 载波是正弦波，频率硬件可调。

java 采用Websocket实现web实时通讯功能，包括mysql数据库文件与视频

内含雷达系统设计MATLAB仿真的pdf和代码，主要包括：雷达基础导论，雷达检测，雷达波形，雷达模糊函数，脉冲压缩，面杂波与体杂波，动目标显示和杂波抑制，相控阵，目标跟踪，电子对抗，雷达截面积，高粉笔啊率战术合成孔径雷达，信号处理等。

The Verilog® Hardware Description Language (Verilog HDL) became an IEEE standard in 1995 as IEEEStd 1364-1995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in astandard textual format for a variety of design tools, including verification simulation, timiThe clear directive from the users for these three task forces was to start by solving some of the followingproblemsConsolidate existing IeeE Std 1364-1995Verilog generate statementMulti-dimensional arraysEnhanced Verilog file i/oRe-entrant tasksStandardize Verilog configurationsEnhance timing representationEnhance the vpi routinesAchievementsOver a period of four years the 1364 Verilog Standards Group(vsg) has produced five drafts of the lrmThe three task forces went through the EEe Std 1364-1995 lRM very thoroughly and in the process of consolidating the existing Lrm have been able to provide nearly three hundred clarifications and errata for theBehavioral, ASIC, and PLI sections. In addition, the vsg has also been able to agree on all the enhance-ments that were requested (including the ones stated above)Three new sections have been added. Clause 13, "Configuring the contents of a design, deals with configuration management and has been added to facilitate both the sharing of verilog designs between designersand/or design groups and the repeatability of the exact contents of a given simulation session Clause 15Timing checks, "has been broken out of Clause 17, "System tasks and functions, "and details more fullhow timing checks are used in specify blocks. Clause 16, "Backannotation using the Standard Delay Format(SDF), addresses using back annotation(IEEE Std 1497-1999)within IEEE Std 1364-2001Extreme care has been taken to enhance the vpi routines to handle all the enhancements in the behavioraland other areas of the lrm. minimum work has been done on the pli routines and most of the work hasbeen concentrated on the vpi routines. Some of the enhancements in the vpi are the save and restart simu-lation control, work area access, error handling, assign/deassign and support for array of instances, generateand file 1/0Work on this standard would not have been possible without funding from the cas society of the ieee andOpen verilog InternationalThe IEEE Std 1364-2001 Verilog standards Group organizationMany individuals from many different organizations participated directly or indirectly in the standardizationprocess. The main body of the Ieee Std 1364-2001 working group is located in the United States, with asubgroup in Japan (EIAJ/1364HDL)The members of the IEEE Std 1364-2001 working group had voting privileges and all motions had to beapproved by this group to be implemented the three task forces focused on their specific areas and theirrecommendations were eventually voted on by the Ieee Std 1364-2001 working group

本资源主要内容：二次规划师非线性优化中的一种特殊情形，它的目标函数是二次实函数，约束函数都是线性函数。由于二次规划比较简单，便于求解（仅次于线性规划），并且一些非线性优化问题可以转化为求解一些列的二次规划问题，因此二次规划的求解方法较早引起人们的重视，称为求解非线性优化的一个重要途径。二次规划的算法较多，本文仅介绍求解等式约束凸二尺规划的拉格朗日方法以及求解一般约束凸二次规划的有效集方法。本资源包含：《求解二次规划问题的拉格朗日及有效集方法》文档以及文档所用到的所有Matlab代码，非常适合初学者学习和研究！