Matlab三次指数平滑算法

多摩川编码器读取程序，支持多摩川ADM485协议，在STM32F4上实验读取TS5668N21成功。

【实例简介】讲述PCB缺陷检测的论文，很好，很好，很强大的哦

IC设计经典教材，《专用集成电路设计实用教程》专用集成电路设计实用教程虞希清编著大學出瓶社图书在版编目(CIP)数据专用集成电路设计实用教程/虞希清编著.一杭州:浙江大学出版社,2007.1ISBN978-7-308-05113-2专..Ⅱ.虞..Ⅲ.集成电路一电路设计一高等学校一教材Ⅳ.TN402中国版本图书馆CIP数据核字(2006)第165341号专用集成电路设计实用教程虞希清编著任编辑张真封面设计张真出版发行浙江大学出版社(杭州天目山路148号邮政编码310028)(E-mail:zupress@mail,hz,zj.cn)(网址http://www.zjupress.com排版杭州好友排版工作室印刷杭州浙大同力教育彩印有限公司开本787mm×1092mm1/16印张18.25字数467千印数2001-3000版印次207年1月第1版2007年7月第2次印刷书号ISBN978-7-30805113-2定价38.00元版权所有翻印必究印装差错负责调换内容提要在现代的IC设计中,工程师们广泛地使用数字电路的逻辑综合技术。工程师们使用RTL代码和IP描述设计的功能,进行高级设计,用综合工具对设计进行编辑和优化,以实现满足设计目标的电路。根据多年为客户进行技术培训,技术支持和IC设计的经验,笔者编写了本书。书中主要介绍了IC设计的基本概念,设计流程和设计方法,并就工程师们在设计中常见的问题,提供了解决方法。本书的特点是实用性强全书共分九章,第一章概述EC设计的趋势和流程;第二章介绍用RTL代码进行电路的高级设计和数字电路的逻辑综合;第三章陈述了IC系统的层次化设计和模块划分;第四章详细地说明如何设置电路的设计目标和约束;第五章介绍综合库和静态时序分析;第六章深入地阐述了电路优化和优化策略;第七章陈述物理综合和简介逻辑综合的拓扑技术;第八章介绍可测性设计;第九章介绍低功耗设计和分析本书的主要对象是IC设计工程师,帮助他们解决IC设计和综合过程中遇到的实际问题。也可作为高等院校相关专业的高年级学生和研究生的参考书。前言本书在 Synopsys公司的逻辑综合培训资料基础上编写而成。从事EDA工作和ASIC设计已有十几年了。在给中港台ASIC设计工程师提供的技术培训和支持中,工程师们曾提出了设计和使用设计工具中遇到的各种各样的问题。教学相长,在和工程师讨论问题、提供解决方案的过程中,我得到了很多的经验和启发。在为用户解决一些实际问题,为他们提供培训后,我曾收到热情的掌声和感谢信。用户的掌声和谢意给了我很大的鼓励和鞭策,使我下决心要编写一本实用的中文版的集成电路设计教程和手册,以答谢用户们的支持和帮助。本书讲究实用性,希望其中的内容能帮助ASIC设计工程师清楚明了IC设计的基本概念,IC设计的流程,逻辑综合的基本概念和设计方法,解决进行IC设计时和工具使用时所遇到的问题。全书共分九章,第一章概述IC设计的趋势和流程;第二章介绍用RTL代码进行电路的高级设计和数字电路的逻辑综合;第三章陈述了IC系统的层次化设计和模块划分;第四章详细地说明如何设置电路的设计目标和约束;第五章介绍综合库和静态时序分析;第六章深入地阐述了电路的优化和优化策略;第七章陈述物理综合和简介逻辑综合的拓扑技术;第八章介绍可测性设计;第九章介绍低功耗设计和分析本书的主要对象是IC设计工程师,帮助他们解决IC设计和综合过程中遇到的实际问题。也可作为高等院校相关专业的高年级学生和研究生的参考书。在本书的编写过程中,得到了 Synopsys中国区高级技术经理常绍军先生的大力支持。常绍军先生、资深的应用技术顾问李昂先生和冯源先生审阅了本书,并提出了宝贵的意见和建议。在此,表示衷心的感谢。在本书编写过程中,得到了全家的支持,深表谢意!由于时间仓促,知识水平有限,书中难免有不足和错误之处,敬请各位专家,IC设计工程师和同行们批评指正,不胜感激。来函可发电子邮件( Email: victory_snps@ yahoo.com.hk)。虞希清2006年11月于 Synopsys香港目录第一章集成电路设计概论1.1摩尔定律………………∴…………11.2集成电路系统的组成1.3集成电路的设计流程第二章数字电路的高级设计和逻辑综合132.1RTL硬件描述语言设计132.1.1行为级硬件描述语言( Behavioral Level hdi)132.1.2寄存器传输级硬件描述语言( RTL HDI)172.1.3结构化硬件描述语言( Structure HDL)………………………………232逻辑综合(L。 gic Synthesis)…………………272.2.1逻辑综合的基本步骤…282.2.2综合工具 Design Compiler302.2.3目标库和初始环境设置鲁·自自音甲·是着音鲁备.··非曲●d■···●····第三章系统的层次化设计和模块划分353.1设计组成及 DC- Tcl…·自音···········日·········.···卡器日音是·晶自鲁bt·。……353.1.1设计物体( Design Object)鲁音自353.1.2 DC - Tcl简介香看·鲁·鲁·鲁.鲁自春3.2层次( Hierarchy)结构和模块划分( Partition)及修改463.2.1层次结构的概念463.2.2模块的划分…息鲁483.2.3模块划分的修改·看。51第四章电路的设计目标和约束…°。●看。面●554.1设计的时序约束…普·非鲁·鲁击曲■554.1.1同步( Synchronous)电路和异步( Asynchronous)电路…4.1.2亚稳态( Metastability)574.1.3单时钟同步设计的时序约束…血D。e574.1.4设计环境的约束724,1.5多时钟同步设计的时序约束…………794.1.6异步设计的时序约束832专用集成电路设计实用教程4.1.7保持时间( Hold Time)854.2复杂时序约束看香鲁e鲁曲鲁。自鲁自。a。自鲁自。鲁4.2.1多时钟周期( Multi-Cycle)的时序约束874.2.2门控时钟的约束904.2.3分频电路和多路传输电路的时钟约束鲁·看看看鲁924.3面积约束……………………………96第五章综合库和静态时序分析…985.1综合库和设计规则···········.······.··4·a·.·····◆···—985.1.1综合库……5.1.2设计规则1075.2静态时序分析5.2.1时序路径和分组1125.2.2时间路径的延迟1145.2.3时序报告和时序问题的诊断鲁·.···.·自击击合音。甲。。。●。。●……115第六章电路优化和优化策略…1206.1电路优化..···4····;··.·.·.·.·a·a·;··1226.1.1 Synopsys的知识产权库- Design Ware1236.1.2电路优化的三个阶段………………………1266.2优化策略…………1346.2.1编辑策略垂由d垂……1356.2.2自动芯片综合( Automated Chip Synthesis)………………………………1416.3网表的生成格式及后处理144第七章物理综合1487.1逻辑综合(L。 gic Synthesis)遇到的问题……………………1487.2物理综合( Physical Synthesis)的基本流程鲁鲁自谁…………………………1517.3逻辑综合的拓扑技术( Topographical Technology)…………162第八章可测试性设计…1748.1生产测试简介…………1748.2可测试性设计鲁D曹吾音·非·自·········着4鲁4鲁是1768.2.1物理瑕疵和故障模型1768.2.2D算法( D algorithm)1788.3测试协议( Test protocol)1858.4测试的设计规则·●鲁q鲁·音鲁鲁D鲁香曹音音音·自自··。·非鲁曲··●1908.4.1可测试性设计中的时钟信号1908.4.2三态总线和双向端口的测试。非……………………198录8.5门级网表可测试问题的自动修正2048.6扫描链的插入2088.7可测试设计的输出和流程2228.8自适应性扫描压缩技术………225第九章低功耗设计和分析2299.1工艺库的功耗模型…………2319.2功耗的分析…鲁鲁鲁……………2379.3低功耗电路的设计和优化2519.3.1门控时钟电路25293.2操作数分离………2619.3.3门级电路的功耗优化●·4·■D鲁曹春击自由2669.3.4多个供电电压( Multi-VDD)…2749.3.5电源门控………276参考文献……………………281第一章集应电路设计概记集成电路( Integrated Circuits)是现代电子设备的重要组成部分。因此,成功设计集成电路对整个电子信息技术产业的发展起到重要的作用。由于科技的发展,半导体芯片的集成化程度越来越高,设计的系统越来越复杂,规模越来越大,设计的性能越来越髙,功耗也越来越大,这些不断地给芯片设计工程师和电子设计自动化( Electronics Design Automation,简称EDA)厂商提出新的课题和挑战。1.1摩尔定律摩尔提出著名的“摩尔定律”已经40多年了。1965年4月,摩尔在《电子学( Electronics)》杂志上发表文章预言,半导体芯片上集成的晶体管数量将每年翻一番。1975年,他又提出修正说,芯片上集成的晶体管数量将每两年翻一番。晶体管数量MOORES LAWIntels Tanuma 2 Processo1000000000ante△nmtele Pentium Pr100000000Intels Pentium m Processoitels Pentium Pro10000000Intelstuma Printels*v Proces1000000Intel388 pre28610000080801000080084004●100019701975198019851990199520002005年度图1.1.1图1.1.1为在过去25年, ntel CPu中晶体管增长的情况。集成电路的规模不断地稳

STM32中文固件库+中文芯片手册(完全版)芯片手册：STM32F10XX 2009年6月第九版，共754页！固件库： 中文版 共781页！打包下载，估计应该是比较全的了。

MTK原厂参考设计，IOT应用。MT2503D芯片是基于ARMv7和采用高集成度系统级封装的物联网芯片平台，支持高精度全球卫星导航系统（GNSS）、蓝牙3.0和2G基带，适用于功能简单的移动设备、安全或工业应用等领域。

应用背景与功能目前，中小学生的学习负担均较重。新知识多，作业量大。对于孩子来说，难免有一些消化不了的东西。在此情况下，如不能及时地把所欠缺的知识补起来，势必造成恶性循环，不理解的东西越压越多。家教可以有针对性地单独授课，学生学习的效果较好，越来越多的家长给孩子选择了请家教。为了找到合适的家教，出现了很多的家教中介，但信息的共享方面还是互联网更强，于是越来越多的家教网站产生了。必备知识注意：如果你是首次接触ASP.NET 2.0，那么请先阅读本书第3章关于ASP.NET 2.0新特性的内容，否则你可能会感觉像在云里雾里。学习过ASP.NET 2.0

MCP2515的FPGA驱动程序，使用Verilog编写，波特率由用户根据需要自行配置，目前只支持标准帧的收发

PICMG microTCA.0 Specification RC1.0ContentsIntroduction and objectives1.1 Overview1.2 Introduction1.2.1S1.2.2 MicroTCa implementation options1画1-21.2.3 Design goals1-21.2.4 Elements of microtca1-312.5 Theory of operation……着1国面1面日正1-81.3 Micro TCA enclosure types191.3.1 Single Shelf implementation191.3.2 TWo Tier mⅸ ed Width Shelf implementation.…….….….….….….….…....1-101.3.3 Two-Tier fixed Single Width Shelf implementation ....................1-101.3.4 Back-to-Back Shelf implementation.1-101.3.5 Cube Shelf implementation..1-101.3.6 Pico Shelf implementations1111.3.7 Other implementation options1111.4 Application examples1-1114.1 Base station…1-111.42 Router1-121.4.3∨ olP node.….1-121.4.4 Other Telecom Network applicationsE画1-121.4.5 Enterprise applications1-131.4.6 Other applications.....1-131.4.7 Consumer applications1-131.5 Special word usage1-131.6 Conformance1-141.7 Dimensions1-141.8 Regulatory guidelines1-141.9 Reference specifications1.10 MicroTCA0 Specification contributor……1-151-161.11 Name and logo usage1-161.12 Intellectual property……1-171.12.1 Necessary claims1,,面,国国,,国面正∴1-181.12.2 Unnecessary claims11181.12. 3 Third party disclosures1-181.13 Glossary1-192Mechanical2-12.1 Mechanical overview∴………….2-12.1.1 Terminology…2-22.1.2 Typical arrangement examples2-22.2 Dimensions, tolerances, drawing symbols, and nomenclature2-62.3 Mechanical concept2-82.4 AdvancedMC Module orientation, location, and positioning2-1624.1 Module orientation.2-162.4.2 Module positioning, horizontal--mandatory2-172.4.3 Module positioning, vertical-mandatoryU.882-192. 4. 4 Module positioning, depth--mandatory,.42-21PICMG( Micro TCAO Specification Draft RC1. 0, May 26, 2006Do not specify or claim compliance with this Draft Specification2.5 Slot detail dimensions2-222.5.1S|ot..2-222.5.2 Slot configurations, subdividing Slots2-222.5.3 Card guide, Strut, and Card Guide Support Plate(CGSP)…………2232.5.4 Optional Subrack attachment plane2-322.5.5 AdvancedMC Module--optional locking………………………2-342.6 Backplane2-3627 Subrack dimensions2-412.7.1 Mandatory Subrack2-422.8 Shelf2-472.8. 1 Shelf types.2-482.8.2 Shelf width and height…...…2-492.8.3 Shelf depth2-492.8.4 Air filter provision2-502.8.5 ESD wrist strap interface2-502.8.6 Shelf alarm LEDs2-512.9 Cable management2-522. 10 Power entry /Power Module2-562.10.1 Power Module pcb dimensions2-582.10.2 Power Module component height1·面2-632.10.3 Power module face plate2-642.10. 4 Power Module handle/Latch mechanism.2672.10.5 Power module lEDs2-672. 10.6 Power Module EMc gasketing2-672.10.7 Power Module satety covers2-672.10 8 Power module labels2-682.10. 9 Power Module Backplane Connector2-682.11 MCH Module2-692.11.1 Module types2-692.11.2 MCH PCB dimensions.2-702.11.3 MCH Subrack slot details2-772.11. 4 Plug Connector.2-792.11.5 Sequencing and contact area2-812.11.6 MCH positioning2-812. 12 Air flow management面2-822.13 Auxiliary Connector(Zone 2 and zone 3)keying2-832.13.1 Component keep- in height2-842.13.2 Connector keep-in height2-842.133 Keying block…2-852.13.5 AMC0 electrically compatible keying block2.13. 4 Keying block with electrical connections2-86.2-872.14 MicroTCa cube2892.15 MicroTCA Pico2.16 Microtca filler pane的∵面1面面,面2-902-902.17 Cooling Units(CUs)2-912.18 Subrack/Shelf/Cube/Pico performance.2922. 18.1 Load carrying2-922.18.2 Insertion cycles2922.18.3ESD2-922.18.4EMC2-93PICMG MicroTCA. 0 Specification Draft RC1.O, May 26, 2006Do not specify or claim compliance with this Draft Specification2. 18.5 Safety2-932.18.6 Physical Slot and Tier numbering2932.19 Subrack/Shelf environmental2-962.19. 1 Subrack shock and vibration2-962.19.2 Earthquake.........2-962.19.3 Flammability2-962.19.4 Atmospheric2-962. 19.5 Thermal2-972.19.6 Acoustic∴…………………2972.19.7 Surface temperatures2-972.20 References2-973 Hardware platform management3-13.1 Overview3.1.1 Micro Tca Carrier model3-13.1.3 Relationship with IPMI, AdvancedMC, and AdvancedTCA.3.1.2 MicroTCA management architecture3-23-73.1.4 Key differences from PICMG 3.0 and AMC.0 specifications..........3-73.1.5 PICMG properties and FRU Device ID assignments3-93.2 Management-related interconnects3-113.2.1 AdvancedMc interconnects3-113.2.2 Power Module and Cooling Unit interconnects3.2.3 Guidelines for OEM Module interconnects and management3-133-143.2.4 Carrier FRU Information device requirements.3-153.25 Microtca carrier interconnects3-193.3 Carrier Manager.…….…..…...…3-203.3.1 MCH Face Plate indicators3-223.3.2 Payload Interface3-223.3.3 Carrier Manager IP address3-223.3.4 IPM event support∴3-243.3.5 Redundant MCH operation3-253.3.6 Addressing3-263.3.7 Carrier number3-293.3.8 Location information34 Shelf Manager…3-383. 4.1 Shelf Manager configuration options383.4.2 Differences from the AdvancedTca shelf Manager3-403.4.3 Shelf-Carrier Manager Interface翻套国画1面,国面,1面D国画面国3-423.4.4 Shelf Manager IP addre3-433.5 MCMC requirements3453.6 EMMC requirements3-463.7 Operational state management3-483.7.1 Carrier Manager start up……….….….….………..……3483.7.2 Shelf Manager actions on Carrier detection3-483.7.3 Normal Shelf operation1B面面国B3-483.7.4 Abnormal situation handling3-4938 Power management.……3-493.8.1 Power clapping国面3-503.8.2 Micro T CA Carrier Power Management records.3-513.8.3 Early power management356PICMG( Micro TCAO Specification Draft RC1. 0, May 26, 2006Do not specify or claim compliance with this Draft Specification3.8.4 Normal power management.3-573.8.5 Power management commands and sensors3-593.8.6 Abnormal power condition handling3-673.9 Cooling management3-693.9.1 Fan geography.…3-703.9.2 Cooling control…3-713.9.3 Normal cooling operation3-723.9.4 Abnormal cooling operation3-733.9.5 Fan tachometer sensors3-733.9.6 Temperature sensors翻画1国翻B1B…3-733.10 Electronic Keying3-743.10.1 Micro TCA Carrier point-to-point connectivity information3-753.10.2 Module point-to-point connectivity information.3-773.10.3 AMC Port state commands3-783.10.4 Clock b- Keying……3-783.11 Telco alarm management3-73. 12 System Event log…………3-863.13 Sensor management3-863.13.1 Guidelines and requirements for fru sensor events3-863.13.2 MCMC SDR requirements.3-873.13.3 EMMC SDR requirements3-883.13.4 Carrier Manager SDR requirements3-883.14 fru Information.3-913. 14.1 EMMC FRU Information3-913. 14.2 MCMC FRU Information3-913.143 Carrier FRu Information3-923. 14.4 Shelf fru information面国面国面3-923.15 PMI message bridging……….3-933.15.1 Message bridging process3-933.16 PMI functions and command3-943. 16.1 Required IPMI functions..3-953.16.2 Command assignments3-973.17 FRU records, sensors and entity Ids∴3-1084 Power…4-14.1 Overview4-14.2 Loads on the Power Subsystem4-24.2.1 Microtca carrier hub(MCH),………,………………………24-24.2.2 Cooling Units4-74.2.3 Advanced mezzanine cards4-104.3 Power architecture4-134.3.1 Basic functionality4-134.3.2 Partitioning of the Power Subsystem:.::a:.4-154.3.3 Power sources4-154.3. 4 Power Subsystem redundancy4-164.3.5 System Grounding considerations4-214.3.6 Power distribution and backplane considerations4-234.4 Control and monitoring of the Power Subsystem4-2444.1 PM-EMMCs4-244.4.2 Geographic Address4-24PICMG MicroTCA. 0 Specification Draft RC1.O, May 26, 2006Do not specify or claim compliance with this Draft Specification4.4.3|PMB-04-2444.4Ps1[S|o#4-254.4.5EN[Slof]#,…4-2544.6 PWRON_[Sot]…4-254.4.7PSPM#4-2644.8 PM-EMMC watchdog timer……4264.4.9 Power Module oK4-2744.10 Power module reset4-274.4.11 System power-up4-274.4.12 Input voltage sensors1国面面量面1国面4-294.4.13 Temperature sensors4-294414 Power module extraction switch4-304,415 Blue lED4-304.4.16LED14-314 4.17 Other leds4-314.5 Connectors4-314.5. 1 Power Module Output Connector4-324.5.2 Power Module Input Connectors81国面面4-324.6 Single-Width,Fu‖- Height Power Module…∴4-334.6.1 Inputs4-344.6.2 Outputs4-354.6.3 Bulk supply current limit4-384.6.4 Control and monitoring………………………4-384.6.5 Redundancy4-384.6.6 Mechanical4-4546.7 Thermals.8...8.88.84-45画·面4.6.8 Regulatory.4-4547 Other mechanical considerations…4-464.7.1 Double-Width form factor4-464.7.2 Form factors other than Full-Height4-464.8 Power source considerations.4-464.8.1 DC power feeds4-474.8.2 AC power feeds4-554.9 References4-605 Thermal5.1 Overview5-15.2 AMC. 0 Modules and microtCa国着画5-15.3 AMC.0 Carriers and microtca5.4 Subrack slot5-25.5 Airflow path5.6 AMC.0 Modules and power dissipation.5-35-35.7 MicroTCA system cooling configuration……….….….…....545. 8 Air distribution in a slot5-45.9 Air inlet and exhaust5-55. 10 Slot cooling capability5-55. 11 Module cooling requirements●5.12 Standard air.5-75.12.1 Derivatie5.122 Barometric changes due to weather....…...……….57PICMG( Micro TCAO Specification Draft RC1. 0, May 26, 2006Do not specify or claim compliance with this Draft Specification5.13 Slot impedance curve.5-85.14 Slot fan flow curve5.15 Cooling Unit failure5-85.16 Filters5.17 System sensors….…….….……5-95.18 Thermal and operating environment5-105.19 Thermal and cabling5-105.20 Simulation and impedance testing5-105.20.1 AdvancedMC/MCH reference Module..5-115.20.2 Power Unit reference module∴5-125.21 Simulation environment5.22 Thermal dynamic modeling5-135.23 Fluid networking modeling5.24 Acoustic noise5-135.25 Surface temperature5-145.26 Design recommendations5-155.27 Cooling limitations and examples..5-175.28 References1面5-226 Interconnect6-16.1 Introduction.…6-16.2 Fabric interface6.2.1 Backplane fabric interface support requirements6-26.2.2 MCH fabric interface support requirements6.3 MCH Specific Interfaces6-46.3.1 MCH update Channel interface6-46.3.2 MCH cross-over Channel interface.6-56. 3. 3 MCH PWR ON interface6-66.3.4 Inter-MCH IPMB-L interface6.4 Synchronization clock interface6.4.1 Signal descriptions6-86. 4.2 Clock architectures6-96.4.3 Non-Telecom and Telecom clocks6-136.5 JTAG interface.…6-136.5.1 JSM Overview6-146.5.2 JSM Signaling Overview6-166.5.3 JSM Interface to mch16.54 JSM Interface to mch2.……6-186.5.5 JSM Interface to Advancedmcs.6-196.5.6 JSM Interface to Power modules.6-226.5.7 JSM Master mode selection6-236.5.8 JSM Interface to External tester..6-246.5.9 MCH JTAG6-266.5. 10 Power module jtAG6-276.6 MicroTCA Interface topologies1画6-276.6. 1 Topology models6-286.6.2 Correlation to AdvancedMc fabric regions6-296.7 MCH Connector pin allocation6-306.7.1 Pin naming conventions6-316.7.2 Fabric interface naming conventions6-31PICMG MicroTCA. 0 Specification Draft RC1.o, May 26, 2006Do not specify or claim compliance with this Draft Specification6.7.3 Synchronization clock interface naming convention6-316.7.4 MCH Connector pin list……………6-326.8 System examples.6-386.8. 1 Redundant MicroTCA system6-386.8.2 Variant redundant microtca interconnect6-416.8.3 Non-redundant MicroTCA system6-45Connectors7-17.1 General information7-17.2 AdvancedMC Backplane Connectors7-17.2.1 AdvancedMC Backplane Connector pin list7-27.2.2 AdvancedMC Backplane Connector dimensions7-27.2.3 Advancedmc backplane connector pcb layout∴7-67. 2. 4 AdvancedMC Backplane Connector electrical characteristics7-107.2.5 AdvancedMC Backplane Connector high-speed characteristics7-147.2.6 AdvancedMC Backplane Connector mechanical characteristics7-187.3 Micro TCa Carrier hub connectors7-197.3.1 Micro TCA Carrier Hub Connector pin list7-197.3.2 Micro TCA Carrier Hub mating interface design7-207.3.3 Micro TCA Carrier Hub backplane connector7-227.3. 4 Micro TCA Carrier Hub Connector Backplane PCB layout7-237. 3.5 Micro tca Carrier Hub connector electrical characteristics7-247.3.6 Micro TCA Carrier Hub Connector high-speed characteristics7-2573.7 Micro tCa Carrier hub connector mechanical characteristics7-297.4 Power Module Output Connector7.4.1 Power Module Output Connector pin list and mating sequence7-317.4.2 Power Module Output Connector dimensions7-327. 4.3 Power Module Output Connector Backplane PCb layout7-347.4.4 Electrical characteristics for power Module output connector.7-367.4.5 Power Module Output Connector mechanical characteristics7-397.5 Power Module Input Connector7.5.1 Power Module Input Connector pin list and mating sequence7-417.5.2 Power Module Input Connector dimensions7-427.5.3 Electrical characteristics for Power Module Input Connector7-477.5.4 Power Module Input Connector mechanical characteristics7-517.6 AdvancedMC Auxiliary Connector7-537.7 Test schedule7-547.7.1 Specimen measurement arrangements7-547.7.2 Test schedule tables.7-647. 8 References.7-798 Regulatory requirements and industry standard guidelines8-18.1 Regulatory……8-18.1.1 Safety8-18.1.2 Electromagnetic compatibility..……………8-28.1.3 Ecology standards.8-28.2 Telecommunications industry standards requirements8-38. 2. 1 EMC/safety requirements for the telecommunications industry.......8-38.2.2 Environmental requirements for the telecommunications industry ..............8-48.3 Reliability/MTBF standards8-7PICMG( Micro TCAO Specification Draft RC1. 0, May 26, 2006Do not specify or claim compliance with this Draft Specification8.4 Cross reference list8.5 FRU test guidelines∴8-78.5. 1 FRU safety test8-88.5.2 FRU EMC testing.8-88.5.3 FRU environmental testing8-9a Module mis-insertion considerationsA-1A 1 MCH Module mis-insertion combinationsA-2A 2 AdvancedMc module mis-insertion combinationsA-5A3 Power management implicationsA-8A 4 System management implicationsA-8A.4.1 Optional MMC instance on MCH ModuleA-9A.4.2 Using an AdvancedMC in an MCH SlotA-13A.4.3 Using an mch in an AdvancedMc SlotA-15A.4.4 Detecting mis-insertionsA-16A.5 Hardware implicationsA-1A. 5. 1 GNd pins at same locations........A-20A.5.2 PSO# and PS1# pins at same locationsA-23A.5.3 PWR and MP pins at same locationsA27A.5. 4 PWR ON pinA-29A.5.5 Ga[2: 0] pins at same locations道1面4…A-31A.5.6 ENABLE# pin at same locationA-35A.5.7 SDA L and SCL L pinsA-37A 5.8 JTAG pinsA-38A 5.9 Cross-over pinsA-39A.5. 10 TMREQ#, 12C SDA, and I2C SCL pins…A-39B Requirement list….B-1PICMG MicroTCA. 0 Specification Draft RC1.O, May 26, 2006Do not specify or claim compliance with this Draft Specification

1、Xue Mei 的 Robust Visual Tracking using L1 Minimization；2、有代码有论文，也有相关论文。3、代码有大量的中文介绍。不同于其他的源代码。非常适合初学者。4、希望能一起交流学习

三种esprit算法的doa估计matlab实现。参考张贤达《通信信号处理》的算法。包括两种普通esprit和TLS_esprit算法。经检查无误。