基于STM32的双向DC-DC变换器的设计与实现
本系统主要由 BUCK 降压模块、BOOST 升压模块、测控模块、辅助电源模块组成。其中BUCK 降压模块和BOOST 升压模块的驱动选用具有波形互补的可编程芯片IR2104、电流采样选用TI 公司专用高边电流采样芯片INA282；测控模块采用低功耗单片机STM32 对输出电压、输出电流实现闭环PI 控制。系统可以实现：在充电模式下，充电电流在 1～2A范围内步进可调且步进值为 0.05A，电流控制精度 1.30%左右；充电电流变换率为 0.87%；充电效率可达到 97.11%，具有测量、显示充电电流以及过充保护功能。在放电模式下，放电效率可达到96.54%且电压能保持在 30V目录第一章绪论1.1课题背景·*······*···*·····*···‘1.2双向DC-D变换器的研究意义1121.3国内外研究和应用现状1.4论文主要的研究内容.第二章双向DG-DG变换器拓扑结构的硏究.34662.1双向DC-DG变换器的基本原理与类型2.2双向DC-DG变换器的电路拓扑2.3双向DCDC变换器方案的设计10第三章双向DC-DC变换器硬件电路分析及参数设计.3.1双向DG-DG变换器的硬件电路分析.…123.2BUCK-B00sT电路器件的选择及参数设计3.3电流采样电路分析及参数设计173.4 MOSFET管驱动电路设计183.5辅助电源设计.19第四章双向DG-DG变换器的软件设计4.1软件设计方法214.2主函数程序设计4.3按键模式的识别.224.4恒流恒压模式的设计……第五章双向DG-DG变换器调试、实验结果与分析255.1测试仪器∴255.2测试方法255.3测试实验数据5.4测试结果分析…27第六章总结与展望6.1总结286.2展望.28[参考文献]附录(一):项目课题获奖情况及总体实物图….31附录1.1项目课题获奖情况31附录1.2双向D-DC变换器的总体实物图,34附录(二)程序清单…..35第一章绪论1.1课题背景航天器由若下分系统组成,分为有效载荷和航天器平台两大类。有效载荷主要是直接执行特殊的航天任务,而航天器平台主要由航天器结构和服务与支持系统构成。服务与支持系统主要包括电源裝置、姿态控制裝置、轨道控制装置、无线电测控装置、数据保管等等。因此,电源分系统是极其重要的,它是航大器所有能源供给装置。若电源部分工作不止常,则整体就将失去作用,变为毫无用处,电源重量占航天器重量的15%~25%。分为化学电源、太阳电池电源和核电源三类。日前世界上90%以上的航天器都采用太阳能电池阵构成的光伏电源发电系统。主功率供电回路的额定电压(母线电压)三个等级:(1)低压—28V,适用功率等级:1200W(2)中压——42或50V,适用功率等级:200水平(3)高压—100V或以上,适用功率等级:4000V水平。载人飞船氿道运行高度为300~400Km,轨道周期约为9lmin,其中轨道最长,阴影吋间37min,最短光照时间54min。飞船屯源分系统组成部分如表1所表1飞船电源分系统组成电源名称电源类型配置舱段用途备注太阳电池阵-镉镍待发段、发射段、自主主电源推进舱蓄电池系统运行段向整船供电有留轨仁务需要时,飞留轨电源太阳电池镉都轨道舱留轨使用期间船配置留轨电源,否电池系统不配置返回/着陆返回、着陆、等待期旧锌银蓄电池组返回舱电源供电补充峰值功率、应急飞应急电源锌银蓄电池组推进舱行供电目前,我国的航天电源部分调节器主要依赖于从欧洲等国家进口,需要耗费巨资,对我国载人航天的航天器产生极其不利的影响。因此,具有自主知识产权的电源部分调节器的研制,具有很重要的意义和深远的影响1.2双向DDG变换器的研究意义在传统的太阳能电池阵构成的光伏电源发电系统,传统的蓄电池充、放电模块很难保证太阳能阵在太阳光线充足时产生多余的能量不会导致航天器的过热以及储能装置蓄电池组的过允电,而且功率密度点较大,成木高,系统结构相对复杂。太阳能光伏电源发电系统是将太阳能转换成电能的发电系统,它的主要部件是由太阳能电池组、太阳能控制器、储能装置蓄电池(组)和太阳跟踪控制系统组成。其特点是高可靠性、寿命长以及对环境不产生污染、能独立进行发电且并网运行,受到世界各国电网公司的喜欢,发展前景十分广阔。太阳电池的发电功率通过“分流调节”全部变换为母线功率,一部分直接给负毂供电,另一部分则通过“充电调节”变换为充电功率为储能装置蓄电池组充电;蓄电池组功率通过“放电调节”变换为母线功率。对太阳电池发电功率的使用优先级依次为供电、充电、分流。充电功率可以视作母线的可调负载。太阳能电池光伏电源发电系统工作原理如图1所示。正丹线充电控制放电调节负载太阳能电池太阳能电池分流控制蓄电池组充电阼供电阵负母线图1光伏电源发电系统工作原理双向DC-DC转换器是连接正负母线电压与储能系统(如储能装置蓄电池组)的关键,所以使转换器的效率变髙极其重要。本文提出了一种降低功耗,提高整机效率的方案,使得对双问DCDC转换器的探讨变得更加具有意义。1.3国内外研究和应用现状20世纪后期,太阳能电池阵-储能装置蓄电池组构成的光伏电源发电系统的休积和重量庞大,著名外国学者提出了一种基于BCK/B0OST双向DCDC直流转换器来代替原有光伏电源发电系统的允电、放电模块,从而实现电压的稳定20世纪90年代,中国工程院院士陈清泉教授将基于BUCK/ BOOST双向DC-DC变换器在电动车领域使用,同年,外国专家研制了用大功率的水冷式DC-DC变换器即基于BUCK/ BOOST双向DC-DC直流转换器来驱动电动车,由于基于BUCK/BO0ST双向DC-DC变换器的输入输出电压的忙负极相反,不适合在电动车上应用,因此,他提出了一种基于BUCK-BO0ST级联型的双向DC-DC变换器,变换器的电源输入端与电压输出端的负端共用。经过4年时间,美国著名大学-弗吉尼亚大学教授李泽元开始研究在燃料电池上双向DC-DC变换器的配套应用。由此可见,用于载人航天的航天器电源和电动车辆的技术更新对双向DC-DC变换器的发展具有巨大的推动作用,随着开关直流变换器技术即脉宽调制技术的实现,给双向DCDC变换器的发展带来了曙光。1994年,有一位著名的澳大利亚学者发表论文,总结出几种非隔离型双向DC-DC变换器拓扑结构,主要是在CM0S开关管上反向并联具有快速、低功耗的二极管,且在二极管上反并联CMOS开关管,从而构成非隔离方式的双向DC-DC变换器种类有:BUCK-B0OST变换器、BUCK/B0OST变换器、CUK变换器和SEPI-ZETA变换器2004年,由我国学者张方华博士对推挽正激移相式、级联式、正反激组合式双向DC-DC直流变换器做了深入的研究。提出∫很多新型的应川电路,研究∫其控制模型,采用PI补偿环节的单电压闭环实现了系统闭环稳定。双向DC-DC变换器的硏究是近年来开关电源技术研宄的一个热门话题。2006年梁永春博士探讨了由反激式并联输入、串联输出构成的反激逆变器,提出了种同步整流的控制方案,极大地简化了髙频链逆变器的控制,使得整流二极管的导通损耗大幅度降低,整个电源系统的效率提高到85.8%。1.4论文主要的研究内容要求:设计一种双向DC-DC变换器,实现电池组的充电、放电功能。系统结构如图2所示,电池组由5节18650型、容量2000~3000mAh的锂离子电池串联组成。所用电阻阻值误差的绝对值不大于5%辅助电源测控电路3BS1 Rs-5Q2电双向DCDC池变换电路组RL=302直流稳压电源图2电池储能装置结构框图1.基本要求接通S、S3,断开S2,将装詈设定为充电模式(1)U2=30V条件下,实现对电池恒流充电。保障充电时电流l在1~2A范围内能够步进可调,步进值应≤0.1A,电流的控制精度≥5%。(2)设定1=2A,调整直流稳压屯源输出电压,使U2在2436V范围内变化时,要求充电电流I的变化率不大于1%(3)设定l1=2A,在U2=30V条件下,变换器的效率n1≥90%(4)测量并显示充电电流,在I-1~2A范围内测量精度不低于2(5)具有过充保护功能:设定l1=2A,当U1超过阈值U=24±0.5V时,停止充电。2.发挥部分(1)断开S1、接通S2,将装置设定为放电模式,保持U2=30±0.5V,此时变换器效率n2≥95%(2)接通S1、S2’断开S3’调整直流稳压电源输出电压,使直流电源电4压U在32~38V范围内变化时,双向DC-DC变换器能够自动切换工作模式即可自动切换充放电模式并保持输出电压U2=30±0.5V。(3)在满足要求的前提下简化结构、减轻重量,使双向DC-DC变换器、测控电烙与辅助电澒三部分的总重量不大于500g。(4)其他第二章双向Dc-D变换器拓扑结构的研究2.1双向DCDc变换器的基本原理与类型2.1.1双向DC-DG变换器的基本原理双向DC-DC变换器是把育流电压转换成另一个数值的电压,它是由软件控制导通的CW0S开关管、储能电感、续流二极管、具有滤波作用的电容、负毂等构成的,通过具有滤波功能的负载电路和直流电压时而使开关管时而接通或者时而关断,仗得另一端即负载上得到另一个直流电压2.1.2D0DG变换器的类型目前,国内外将双向DCDC变换器的拓扑结构主要划分为非隔离式和隔离式两大类。非隔离型拓扑的主要有:BUCK降压式、 BOOST升压式、BUCK- BOOST升降压型等拓扑。非隔离型拓扑如图3所示。隔离型拓扑的主要有:止激、反激、推挽、半桥、全桥型变换器(1)隔离型变换DYYYCD(a)BUCK变换器拓扑(b) BOOST变换器拓扑DL(c)BUCK- BOOST变换器拓扑图3非隔离型变换器拓扑以最基木的BUCK降压式变换器和BO0ST升压式变换器为例,介绍其工作原理。BUCK降压式变换器:当CMOS开关管Q接通时,电源Vin通过电感L给电容C充电;当开关管断开时,电感L通过快速、低功耗二极管D续流,电压逐渐降低。此时,电容上的电流由正逐渐降为零,最后变成负向,进而使开关管又一次导通,使得电感上电流增加。其储能电感L上电流波形如下图4所示tImar1-min(a)BUCK电感电流连续时波形(b)BUCK电感电流断续时波形图4BUCK电感电流波形BO0ST升压式变换器:当开关管Q导通吋,电源向电感L储能,电感L电流增加,负载由电容C供电;当开关管Q关断时,电感电流减小,电感电势与输入电压叠加,迫使二极管D导通,一起向负载供电,并同时向电容C充电。其电感电流波形如图5所小7
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索尼 imx274 datesheet
imx274 datesheet，可以对接Hi3519V101，4K，分享一下SONYIMX274LQC-CAbsolute Maximum RatingsItemSymbolRatingsUnitSupply voltage(Analog)1ADD0.3to+3.3VSupply voltage(Digital 1)-0.5to+2.0Supply voltage(Digital 2)DDD20.5to+3.3VInput voltage(Digital)0.3toV。Dp+0.3VOutput voltage(Digital)-0.3toVD2+0.3Guaranteed operating temperature TOPR-30to+75°CStorage guarantee temperatureTSTG30to+80CPerformance guarantee temperature TsPEC10to+60Recommended Operating ConditionsItemSymbolRatingSupply voltage(Analog)VADD2.8±0.1Supply voltage(Digital 1)1.2±0.1VSupply voltage(Digital 2)1.8±0.1Input voltage(Digital)-0.1 to Vopp2+0.11 VADD: VDDSUB, VoDHCM, VoDHPX, VDDHDA, VDDHCP (2.8V power supplyVDDD1: VDDLCN, VDDLSC1 to 2, VDDLPA, VDDLPL1, VoDLPL2 to 3. VDDLIF (1.2V power supply)VDDD2: VDDMIO, VDDMIF (1.8V power supply)SONYIMX274LQC-CUSE RESTRICTION NOTICEThis USE RESTRIC TION NOTICE (Notice )is for customers who are considering or currently using theimage sensor products("Products")set forth in this specifications book. Sony Corporation Sony")mayat any time, modify this Notice which will be available to you in the latest specifications book for theProducts. You should abide by the latest version of this Notice. If a Sony subsidiary or distributor has itsown use restriction notice on the Products, such a use restriction notice will additionally apply betweerou and the subsidiary or distributor. You should consult a sales representative of the subsidiary ordistributor of sony on such a use restriction notice when you consider using the ProductsUse restrictionsThe Products are intended for incorporation into such general electronic equipment as office productscommunication products, measurement products, and home electronics products in accordance withthe terms and conditions set forth in this specifications book and otherwise notified by sony from timeYou should not use the Products for critical applications which may pose a life-or injury-threateningrisk or are highly likely to cause significant property damage in the event of failure of the products. Youshould consult your sales representative beforehand when you consider using the products for suchcritical applications. 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You should review those terms and conditions when you consider purchasingand/or using the ProductsGeneral-0.0. 8SONYIMX274LQC-CContentsDescription---FeaturesDevice structureOptical Black Array and Readout Scan Direction---Absolute Maximum Ratings2233Recommended Operating Conditions---------------USE RESTRICTION NOTICEContentsOptical CePin Configuration------------------Pin description-------------------------458899hen using csl-2When using Sub-LVDS1210 Equivalent Circuit Diagram15Peripheral Circuit19System OutlineWhen using CSl-2When using Sub-LVDSElectrical Characteristics when using cs1-2--------------------------m---------------------------------21. DC Characteristics(CS1-2)a.8..4Current Consumption and Gain Variable Range(CSl-2Supply Voltage and l/O Voltage(CS1-2)2. AC Characteristics(CS1-222INCK, XCLR(CSl-2)22XHS, XVS(Output)(CSI-2)22IC Communication (CSI-2)23DMCKP/DMCKN, DMO(CSl-2Electrical Characteristics When Using Sub-LVDs-------------------m--------------------------1. DC Characteristics(Sub-LVDs)……Current Consumption and gain Variable Range sub-LVDS24Supply Voltage and l/o Voltage(Sub-LVDSLVDS Output DC Characteristics(Sub-LVDS2. AC Characteristics ( Sub-LVDS).........25INCK, XCLR, XVS(input), XHS (input)(Sub-LVDS25Serial Communication(Sub-LVDS)Sub-LVDS Output(Sub-LVDS)26Spectral Sensitivity Characteristics(CS1-2 and Sub-LVDS27Image Sensor Characteristics(CSl-2 and Sub-LVDS)-281. Zone Definition of Image Sensor Characteristics28mage Sensor Characteristics Measurement Method(CSl-2 and Sub-LVDS)1. Measurement conditions2. Color Coding of this Image Sensor and Readout..293. Definition of Standard Imaging Conditions29Setting Registers Using I"C Communication(When Using CSl-2Description of Setting Registers When Using I C communication31Pin Connection of Serial Communication Operation Specifications When Using I"C CommunicationRegister Communication Timing When Using I-C Communication12C Communication Protocol32Register Write and Read33Single Read from Random Location33Single read from current location; iidaiaii:;aaaa“Sequential Read Starting from Random LocationSequential Read Starting from Current Location34Single Write to Random Location35Sequential Write Starting from Random Location35Register Value Reflection Timing to Output Data(CSl-2)36SONYIMX274LQC-CSetting Registers Using Serial Communication (When Using Sub-LVDS)----------------37Setting Registers Using Serial Communication(Sub-LVDS).37Register Value Reflection Timing to Output Data( Sub-LVDS38Register Map…391. Description of Register2. Register Setting for Each Readout Drive Modeeadout Drive Modes( csl-2 and Sub-LVDS)---------------------551. Readout drive modes552. Relationship between Arithmetic Processing and the Number of Output bits in Each Readout Drive ModeImage Data Output Format When Using CSI-2--------------------------58Frame Format (CSI-2)58Frame Structure(CSl-258Embedded Data Line(CSl-2)59CSl-2 serial Output Setting(CSl-2)MIPI Transmitter(CSl-2)62Detailed Specification of Each Mode(CSl-2)---------------631. Horizontal/ Vertical Operation Period in Each Readout Drive Mode(CSl-22. Frame Rate Adjustment(CSl-23. Image Data Output Format CSl-265Vertical Arbitrary Cropping Function(CSl-2)-69Horizontal Arbitrary Cropping Function(CSl-272Electronic Shutter Timing When Using CSI-2------741. SHR, SVR, SMD Setting When Using CSl-2741-1. SHR, SVR Setting(CSl-2)741-2. Electronic Shutter Drive Mode(Csl-2)752. Integration Time in Each Readout Drive Mode and Mode Changes When Using CSl-2762-1. Integration Time in Each Readout Drive Mode(CSl-2762-2. Operation when Changing the Readout Drive Mode(CSl-2772-3. Low Power Consumption Drive in Integration Time When Using Roll ing Shutter Operation(CSl-2)78Image Data Output Format When Using Sub-LVDS--791. Sync Signals and Data Output Timing(Sub-LVDS)““792. Output Range of LVDS Output Data(Sub-LVDS)Detailed Specification of Each Mode(Sub-LVDS)删mHorizontal/Vertical Operation Period in Each Readout Drive Mode(sub-LVDs)..........2. Frame Rate Adjus咖ment(Sub-LVDS)……3. Image Data Output Format ( Sub-LVDS)Vertical Arbitrary Cropping(Sub-LVDS)Horizontal arbitrary cropping function(Sub-LVDS)----m94Electronic Shutter Timing When Using Sub-LVDS961. SHR, SVR Setting(Sub-LVDS)...962. SVR Operation (Sub-LVDS3. Electronic Shutter Drive Mode( Sub-LVDS)974. Integration Time in Each Readout Drive Mode and mode changes When Using Sub-LVDS984-1. Integration Time in Each Readout Drive Mode(Sub-LVDS984-2. Operation when Changing the Readout Drive Mode(Sub-LVDS994-3. Recommended Global Reset Shutter Operation Sequence(Sub-LVDS)1004-4. Interruptive Mode Change(Sub-LVDS4-5. Low Power Consumption Drive in Exposure Time (Sub-LVDS)…102Power-on/off Sequence when using CSI-2---1031. Power-on Sequence(CS2)……1032. Slew Rate Limitation of Power-on Sequence( CSI-21033. Power-off Sequence(CSl-2104Standby cancel sequence when using csl-2--------------------------105Power-on/off Sequence when using Sub-LVDS1161. Power-on Sequence(Sub-LVDS)1062. Slew Rate Limitation of Power-on Sequence(Sub-LVDS).........1063. Power-off Sequence(Sub-LVDS)107Standby Cancel Sequence(Sub-LVDs)------------108SONYIMX274LQC-CSpot Pixel specifications--109Spot Pixel Zone Definition109Notice on White Pixels SpecificationsMeasurement Method for Spot Pixels1111. Black or white pixels at high light1112. White pixels in the dark.3. Black pixels at signal saturated111Spot Pixel Pattern Specifications----------------m---------------------------------------------------112Stain Specifications---113Stain Zone definition113Stain Measurement method.113Relation between Image height and target Cra-----Marking---------mm---------------115Notes on Handling116Package outline ---118List of Trademark Logos and Definition Statements-------------119SONYIMX274LQC-COptical Center(Top View)Package outline10.70±0.1mmPKG lpinM1A1Optical centerM1010See page TBD Package Outl ine" for detailsOptical CenterPin ConfigurationBottom View)lpin index6666δ画δ尚画○●Bottom viewQ§③¤¤意○○○○○○○○10○o⑦A b CE F GMPin configurationSONYIMX274LQC-CPin DescriptionWhen using CS1-2Pin descriptionState inSymbolOADRemarks(CS|-2Standby modeLeave openA2TEST4ATest(No connectionA3VDDHDa Power a Analog power supply (2.8V)A4VDD SUB PowerAnalog power supply(2.8VA5VDDLSC1PowerD Digital power supply(1.2v)A6VssLSC1GNDDDigital GND(1.2V)A7VDDLPL3 Power D Digital power supply (1.2 V)A8VDDLIFowerDigital power supply(1.2v)Leave openB1TEST5ATest(No connectionB2ssHDA GND A Analog GND (2.8V)B3BIASRESResister connectionB4/BGRCapacitor connectionB5GNDD Digital GND (1B6XCLRReset pulse inputB7VssLPL3GNDDigital GND (1.2VB8 VsSLIF1 GND D Digital GND (1.2V)B9DMO4NDigital MiPl outputLow LevelData lane 4connectionB10DMO4P。DDigital MIPl outputLow LevelData lane 4connectionC1TESt3TestLeave open(No connectionC2XCECannect to 1.8 V power supplyLeave openC3TEST1D(No connectionC4TEST2estLeave open(No connectionC5VDDLPAPowerDDigital power supply(1.2v)C6 VDDLPL2 Power D Digital power supply (1.2V)C7 VssLPL2 GND D Digital GND(1.2V)c9DMO2NDigital MIPl outputLow LevelData lane 2connectionData lane 2C10DMO2PDigital MIPl outputLow LevelconnectionD1XHSDDDDHorizontal sync signal outputIf unused xHsleave openD2SDOlest outputLow Leve/ Leave openNo connectionVertical sync signal outpuf unusedⅩVSDleave openD9DMCKND Digital MIPl outputLow LevelClock laneconnectionD10DMCKPDigital MIPl outputLow levelClock LaneconnectionE1SCLDDDc communication clock inputC communication dataE2SDAOinput/outputSONYIMX274LQC-CPinPin descriptionSymbolADState inRemarksNoCS-2Stand by modeE3VSSLCBGNDDigital GND(1.2 V)E8VssLlF2GNDDigital GND(1.2 V)E9DMO1NE10DMO1POFVDDLSC2 PowerF2VssLSC3 PowerDDDDDDADData lane 1Digital MIPl outputLow LevelconnectionData lane 1Digital MIPI outputLow LevelconnectionDigital power supply (1.2 V)Digital power supply (1.2 v)F3VopHCMPowerAnalog power supply(2.8 V)F8INCKInput clockDMO3NDigital MIPl outputData lane 3Low LevelconnectionF10 DMO3PData lane 3Digital MIPI outputLow LevelconnectionG3VssHCPGNDAAnalog GND (2.8V)G8VssLSC2 GND D Digital GND(1.2V)G9VssMIF2 GNDD Digital GND (1.8VG10VoDMIFPowerDDigital power supply (1.8V)H1VDDLCN GND D Digital GND(1.2V)VsSLCNGNDDigital GND (1.2 VH3VopHCPPowerAnalog power supply(2.8VDLO2P( Pin for Sub-LVDS)Leave open(No connectionH9DLO2M000(Pin for Sub-LVDS)Leave open(No connectiH10DLOOP(Pin for Sub-LVDS)Leave open(No connection)VssHPX3 GND AAnalog GND(2.8 V)J3VoDHPXPowerDLO3PADDDAADDAnalog power supply(2.8 V)(Pin for Sub-LVDS)Leave open(No connectionDLO3MO00(Pin for Sub-LVDS)Leave open(No connection)J10DLOOMD(Pin for Sub-LVDS)eave open(No connection)K2VssLPL 1GNDDDigital GND(1.2V)K3 VDDLPL1 Power D Digital power supply(1.2V)K4VoDMIO Power D Digital power supply(1.8V)K5DLO1M(Pin for Sub-LVDS)Leave open(No connectionDLCKM0b「(Pin for Sub-LVDS)Leave open(No connection)Leave openK7DLCKPD(Pin for Sub-LVDS(No connectionLeave openK8DLO9PD(Pin for Sub-LVDS)(No connectionLeave openK9DLO9M(Pin for Sub-LVDS)(No connectionK10DLO5P(Pin for Sub-LVDS)Leave openNo connection
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