TMS320LF2407

STM32F10x与AD7606 并行程序,里面含有全部的程序，值得下载。

dsp 田黎育的课件 讲解比较详细

本人认为真正厉害的黑客不是仅仅精于使用别人开发出来的黑客工具，而是自己利用所学的知识去开发自己想要的工具。况且去下载别人的工具，有时候就上了别人的钩了，很多黑空工具本身就绑定木马，自己黑别人不成，却先被别人黑了。但是要申明一点，我学黑客技术是想做中国的红客，在必要的时候与同好为国民出口恶气...

【实例简介】以太网 控制器 源码 Verilog 源程序，蛮复杂

Silicon Labs EM35x Reference Design with RFX2401C，可以学习到RFX2401C的电路设计方法，像我这样的新手就直接抄了，特别是天线部分，可以套用到其他2.4GHz模块上

基于深度学习的刀具磨损状态监测技术的研究，基于深度学习的刀具磨损状态监测技术的研究

【实例简介】一个Lorenz混沌系统代码，可供学习研究混沌系统的参考，对图像做加密解密处理

员工信息管理系统 C++ Microsoft Office Access 2003内附完整报告，包括数据库，数据流图，需求分析等。

The Verilog® Hardware Description Language (Verilog HDL) became an IEEE standard in 1995 as IEEEStd 1364-1995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in astandard textual format for a variety of design tools, including verification simulation, timiThe clear directive from the users for these three task forces was to start by solving some of the followingproblemsConsolidate existing IeeE Std 1364-1995Verilog generate statementMulti-dimensional arraysEnhanced Verilog file i/oRe-entrant tasksStandardize Verilog configurationsEnhance timing representationEnhance the vpi routinesAchievementsOver a period of four years the 1364 Verilog Standards Group(vsg) has produced five drafts of the lrmThe three task forces went through the EEe Std 1364-1995 lRM very thoroughly and in the process of consolidating the existing Lrm have been able to provide nearly three hundred clarifications and errata for theBehavioral, ASIC, and PLI sections. In addition, the vsg has also been able to agree on all the enhance-ments that were requested (including the ones stated above)Three new sections have been added. Clause 13, "Configuring the contents of a design, deals with configuration management and has been added to facilitate both the sharing of verilog designs between designersand/or design groups and the repeatability of the exact contents of a given simulation session Clause 15Timing checks, "has been broken out of Clause 17, "System tasks and functions, "and details more fullhow timing checks are used in specify blocks. Clause 16, "Backannotation using the Standard Delay Format(SDF), addresses using back annotation(IEEE Std 1497-1999)within IEEE Std 1364-2001Extreme care has been taken to enhance the vpi routines to handle all the enhancements in the behavioraland other areas of the lrm. minimum work has been done on the pli routines and most of the work hasbeen concentrated on the vpi routines. Some of the enhancements in the vpi are the save and restart simu-lation control, work area access, error handling, assign/deassign and support for array of instances, generateand file 1/0Work on this standard would not have been possible without funding from the cas society of the ieee andOpen verilog InternationalThe IEEE Std 1364-2001 Verilog standards Group organizationMany individuals from many different organizations participated directly or indirectly in the standardizationprocess. The main body of the Ieee Std 1364-2001 working group is located in the United States, with asubgroup in Japan (EIAJ/1364HDL)The members of the IEEE Std 1364-2001 working group had voting privileges and all motions had to beapproved by this group to be implemented the three task forces focused on their specific areas and theirrecommendations were eventually voted on by the Ieee Std 1364-2001 working group

简洁使用verilog语言编写的数字时钟，并且可以输入预设时间调整，时分秒分三段描述，简洁明了