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雷达协同干扰策略及干扰方法研究_付昕莹
说明: 这是一篇讲述多雷达协同干扰策略和方法的论文,可参考进行相关研究。(This is a paper on the strategy and method of multi-radar cooperative jamming, which can be referred to for relevant research.)
- 2020-12-03 21:56:07下载
- 积分:1
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algebra-code-for-communication
代数编码纠错编码的经典书籍Richard_E._Blahut(error control code and algebra code;Richard_E._Blahut)
- 2012-02-20 16:14:54下载
- 积分:1
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spectralnull
a document wich explain spectral null codes
- 2012-06-16 00:18:48下载
- 积分:1
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AREPS_IEEE
美国海军开发的雷达传输损耗预测、计算软件AREPS的说明(The Space and Naval Warfare System Center, San Diego has a full spectrum research and development program with a long and proud history of rapidly responding to critical fleet requirements and deploying systems to address these requirements. One such system is the new Advanced Refractive Effects Prediction System (AREPS).)
- 2020-09-02 21:58:08下载
- 积分:1
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802[1].3afPandPP802.3at-2009
802.3af/at标准,POE 供电协议(standard of 802.3af/at)
- 2011-05-28 10:26:46下载
- 积分:1
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program
encoding binary data using non return to zero
- 2017-02-27 14:09:19下载
- 积分:1
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wireless-communication
无线通信经典教材(杨鸿文译),(美)哥德史密斯(Goldsmith,A.)著。(图灵电子与电气工程丛书)(Classic textbook of wireless communication (Yang Hongwen translation), (U.S.) Goldsmith (Goldsmith, A.). (Turing Electronic and Electrical Engineering Series))
- 2012-05-18 11:55:47下载
- 积分:1
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Cluster-Head-Selection-using-a-Two-Level-Fuzzy-Lo
Cluster Head Selection using a Two-Level Fuzzy Logic in Wireless Sensor Networks
- 2012-12-06 17:09:30下载
- 积分:1
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0000PUB-07_Khatir
ANALYSIS OF RECOVERY FROM COMMUTATION FAILURES IN AN HVDC
INVERTER CONNECTED TO A WEAK RECEIVING AC SYSTEM
- 2012-12-10 14:22:32下载
- 积分:1
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TheResearchAndIPDesignOfSMBusBasedSmartBattery
本文研究了SMBus
规范,介绍了典型的基于片上系统(SoC)设计的知识产权核(IP)实现,采用自顶向下
(Top-down)的集成电路设计方法完成了设计,并架构了基于总线功能模型(BFM)的验证平台
完成功能仿真,顺利完成了逻辑综合和时序仿真。FPGA 验证和投片后测试均表明设计具有
良好的性能。(This paper studies the SMBus specification, based on the introduction of the typical system-on-chip (SoC) intellectual property core design (IP) implementation, using top-down (Top-down) of the integrated circuit design methods achieve a design and architecture based on the total Line functional model (BFM) achieve functional verification platform for simulation, successfully completed a logic synthesis and timing simulation. FPGA silicon validation and post-tests show that the design has good performance.)
- 2009-03-26 12:16:53下载
- 积分:1