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clk_freq

于 2020-06-22 发布 文件大小:1KB
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下载积分: 1 下载次数: 1

代码说明:

  时钟分频,通用模块,可以分出任意频率时钟,FPGA Verilog(clock divider fpga verilog)

文件列表:

clk_freq\clk_freq.v, 1172 , 2019-07-24
clk_freq\top.v, 985 , 2019-07-24
clk_freq\说明.v, 131 , 2019-07-24
clk_freq, 0 , 2019-07-24

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