acc.m

JSP+Ext网盘系统，界面漂亮，上传好用，源码完整，请大家先看下截图，EXTJS框架实现的前端界面，结合JSP底层实现的上传内核，上传速度快，支持批量上传，显示上传进度，功能方面虽然不是100%完善，不过已经实现了网盘的基本功能，拿去学习EXT也是很不错的资料。

平滑字体控件 版　　本： 文件大小：388.445Kb 软件语言：简体中文 授权方式：免费版 相关链接：程序演示 -font smoothing controls version : File Size : 388.445Kb software Language : English license : free version Related Links : The process demonstration

MPU6050经过互补滤波和四元数转换为欧拉角 得到稳定的三轴角度(MPU6050 is converted to Euler angles by complementary filtering and four element number to obtain a stable three axis angle)

MySQL创建表格并导入数据，导入的数据是CSV文件的格式。并且说明了如果报错说不能连接MySQL 服务器的情况，说明啦应该怎么解决这个问题。(MySQL creates tables and imports data in the form of CSV files. It also explains how to solve this problem if the error report says that MySQL server can not be connected.)

平台的第一个帖子，测试上传是否可以用。处女贴，请见谅(The first post of the platform is test upload. Maiden paste, please forgive me)

用python实现3D空间散点的连线绘图(Realization of 3D Spatial Spot Connection Drawing with Python)

SPI

pci core altera fpga pci开发设计资料-pci core altera fpga development of design information pci

光孤子传输特性模拟 在光纤通信中，光脉冲信号在光纤中传输的过程中会受到色散、损耗和非线性等作用的影响而不断地发生演化和畸变。脉冲演化的规律遵循非线性薛定谔方程（NLSE）。由于NSLE 在一般情况下无法求得它的解析解，因此通常需采要用数值方法来求解，最终归结于求解归一化的NLSE。本文使用了分步傅里叶方法对归一化NLSE 进行了求解，并模拟了输入为一到三阶双曲正割光脉冲条件下光脉冲传输演变情况。(soliton In optical fiber communications, the optical pulse signals in fiber-optic transmission process will be subject to dispersion, loss and non-linear effects, such as constant evolution and distortion occurs. Pulse to follow the evolution of the law of nonlinear Schrö dinger equation (NLSE). Because NSLE under normal circumstances can not achieve its analytical solution, it normally takes mining use numerical methods to solve, and ultimately attributed to solving normalized NLSE. This article uses the step-by-step Fourier method and normalized NLSE was solved, and analog input for the first-order,second-order and third-order hyperbolic secant optical pulses under the conditions of the evolution of optical pulse transmission.)

基于FPGA的DDS算法的实现，已经通过FPGA的后端仿真实现-FPGA-based algorithm cordic, has passed the back-end FPGA simulation