STATCOM DETAILED MODEL

敏感词处理程序，可以由用户修改敏感词库，无用词库，标点符号词库，最大输入字数(Sensitive word processing program, can be modified by the user sensitive thesaurus thesaurus, useless, punctuation thesaurus, the maximum input words)

俄罗斯方块 vc6编写 界面简洁 窗口自由缩放 -Tetris vc6 prepare concise interface window scaling freedom

中国象棋游戏，该游戏是基于WEB的在线WEB游戏，无需安装任何软件，只要浏览器，便可运行-Chinese Chess Game, which is based on the WEB Games WEB Games online, no need to install any software, as long as the browser, can run

说明：  仿真伪相位编码连续波雷达的信号处理。设码频为 5MHz，伪码周期内码长为511，雷达载频为 10GHz，输入噪声为高斯白噪声，视频输入信噪比为 -15dB，相干 积累总时宽不大于0ms，给出回波视频表达式，脉压和FFT后的表达式；仿真给 出脉压和FFT 后的输出图形；通过仿真说明各级处理的增益，与各级时宽和带宽的关系；仿真说明脉压时多卜勒敏感现象和多卜勒容限及其性能损失（脉压主旁比与多卜勒的曲线）(Simulation of pseudo phase coded CW radar signal processing. Suppose the code frequency is 5MHz, the code length in the pseudo code period is 511, the radar carrier frequency is 10GHz, the input noise is Gaussian white noise, the video input signal-to-noise ratio is - 15dB, the total coherent accumulation time width is not more than 0ms, the echo video expression, the expression after pulse pressure and FFT are given; the pulse pressure and FFT are given by simulation After that, the output graph; the relationship between the gain of each level of processing and the time width and bandwidth of each level through simulation; the phenomenon of Doppler sensitivity, Doppler tolerance and its performance loss during pulse compression (the curve of the ratio of main to side of pulse pressure and Doppler))

管道应力分布，利用ansys mechanical APDL命令流进行计算(Pipeline stress distribution is calculated by using ANSYS mechanical APDL command stream.)

说明：  LL（1）文法的识别，和LL（1）分析表的构造(Recognition of LL(1) Grammar and Construction of LL(1) Analysis Table)

说明：  Its a full simulation of Standard waveport in HFSS with Driven Modal and Driven Terminal Mode that can be used in many other simulations.

多普达P800 RUU直接 刷机 工具`-Dopod P800 RUU Brush tool directly `

论坛源码，采用ACCESS数据库，可不需修改而直接使用-Forum source using ACCESS database, without modification, the use of direct

说明：  Actel 8051 Verilog core