BEM-master

说明：  OFDM仿真，包括仿真图，功率谱，星座图等(OFDM simulation, including simulation diagram, power spectrum, constellation diagram, etc.)

卷积码的Viterbi译码算法仿真程序 要求：递归卷积码，归零处理(Convolutional Codes Viterbi decoding algorithm simulation program requirements : recursive convolutional codes and zeroing treatment)

PCSC APDU specification.

nuclear energie in the industry

微软RIL白皮书。介绍了微软RIL(Radio Interface Layer)的架构和开发所必须具备的知识，包括简介、RIL Modem接口、开发环境、平台实现、测试，以及相关信息(Microsoft White Paper RIL. It introduced Microsoft RIL (Radio Interface Layer) architecture and the necessary knowledge for developer, including the Introduction, RIL Modem interface, development environment, platform, testing, and related information)

关于移动通信中MIMO中的CDD发射分集算法( CDD transmit diversity algorithm on MIMO in the Mobile communication)

【matlab】Clarke信道全向天线和环形天线包络协方差与成型因子关系仿真代码(Simulation code of the relationship between the envelope covariance of the Clarke channel omnidirectional antenna and the ring antenna and the forming factor using MATLAB)

虚拟串口工具，可以在普通电脑上虚拟成对串口，方便进行串口编程的本地调试(Virtual Serial Port Tool, which can be virtual paired serial ports on ordinary computers, facilitates the local debugging of serial port programming.)

说明：  3. 瑞利信道中的调制解调、信道估计： (1) 请推导出单径瑞利信道中的BPSK相干解调的理论误码率性能，并画出比特信噪比与误码率的关系曲线。 (2) 在单径瑞利信道中，请设计一种时分的导引辅助的信道估计方法，用Simulink进行仿真，测量BPSK的误码率性能，画出比特信噪比与误码率的关系曲线，并与理论误码率曲线进行对比。(3. Modulation demodulation and channel estimation in Rayleigh channel: (1) deduce the theoretical bit error rate performance of BPSK coherent demodulation in single-path Rayleigh channel, and draw the relationship curve between bit signal-to-noise ratio and bit error rate. (2) in single-path Rayleigh channel, please design a time-division guidance assisted channel estimation method, Simulink simulation, measure the bit error rate performance of BPSK, draw the relationship curve between bit SNR and bit error rate, and compare with the theoretical bit error rate curve.)

说明：  pi/4-dqpsk-1的verilog工程，实现电脑与FPGA自发自收(pi/4-dqpsk-1,It can realize the self receiving of computer and FPGA)