Final_final_test

  五级流水CPU设计 流水线是数字系统中一种提高系统稳定性和工作速度的方法，广泛应用于高档CPU的架构中。根据MIPS处理器的特点，将整体的处理过程分为取指令（IF）、指令译码（ID）、执行（EX）、存储器访问（MEM）和寄存器会写（WB）五级，对应多周期的五个处理阶段。一个指令的执行需要5个时钟周期，每个时钟周期的上升沿来临时，此指令所代表的一系列数据和控制信息将转移到下一级处理。(Five level flow CPU design)

Final_final_test\ALU.v, 345 , 2017-12-05
Final_final_test\ControlUnit.v, 918 , 2017-11-13
Final_final_test\DtoE.v, 1211 , 2017-12-06
Final_final_test\EqualD.v, 149 , 2017-12-06
Final_final_test\EtoM.v, 697 , 2017-12-06
Final_final_test\FtoD.v, 377 , 2017-12-06
Final_final_test\HazardUnit.v, 1164 , 2017-12-06
Final_final_test\modelsim.ini, 11129 , 2017-12-06
Final_final_test\MtoW.v, 601 , 2017-12-06
Final_final_test\mywork\@a@l@u\verilog.prw, 230 , 2017-12-06
Final_final_test\mywork\@a@l@u\verilog.psm, 4664 , 2017-12-06
Final_final_test\mywork\@a@l@u\_primary.dat, 427 , 2017-12-06
Final_final_test\mywork\@a@l@u\_primary.dbs, 472 , 2017-12-06
Final_final_test\mywork\@a@l@u\_primary.vhd, 333 , 2017-12-06
Final_final_test\mywork\@control@unit\verilog.prw, 825 , 2017-12-06
Final_final_test\mywork\@control@unit\verilog.psm, 13376 , 2017-12-06
Final_final_test\mywork\@control@unit\_primary.dat, 1324 , 2017-12-06
Final_final_test\mywork\@control@unit\_primary.dbs, 1803 , 2017-12-06
Final_final_test\mywork\@control@unit\_primary.vhd, 628 , 2017-12-06
Final_final_test\mywork\@dto@e\verilog.prw, 691 , 2017-12-06
Final_final_test\mywork\@dto@e\verilog.psm, 16872 , 2017-12-06
Final_final_test\mywork\@dto@e\_primary.dat, 1193 , 2017-12-06
Final_final_test\mywork\@dto@e\_primary.dbs, 1872 , 2017-12-06
Final_final_test\mywork\@dto@e\_primary.vhd, 1517 , 2017-12-06
Final_final_test\mywork\@dto@m\verilog.prw, 443 , 2017-12-06
Final_final_test\mywork\@dto@m\verilog.psm, 7816 , 2017-12-06
Final_final_test\mywork\@dto@m\_primary.dat, 535 , 2017-12-06
Final_final_test\mywork\@dto@m\_primary.dbs, 892 , 2017-12-06
Final_final_test\mywork\@dto@m\_primary.vhd, 761 , 2017-12-06
Final_final_test\mywork\@equal@d\verilog.prw, 191 , 2017-12-06
Final_final_test\mywork\@equal@d\verilog.psm, 2696 , 2017-12-06
Final_final_test\mywork\@equal@d\_primary.dat, 230 , 2017-12-06
Final_final_test\mywork\@equal@d\_primary.dbs, 365 , 2017-12-06
Final_final_test\mywork\@equal@d\_primary.vhd, 257 , 2017-12-06
Final_final_test\mywork\@eto@m\verilog.prw, 480 , 2017-12-06
Final_final_test\mywork\@eto@m\verilog.psm, 9424 , 2017-12-06
Final_final_test\mywork\@eto@m\_primary.dat, 668 , 2017-12-06
Final_final_test\mywork\@eto@m\_primary.dbs, 1092 , 2017-12-06
Final_final_test\mywork\@eto@m\_primary.vhd, 804 , 2017-12-06
Final_final_test\mywork\@fto@d\verilog.prw, 290 , 2017-12-06
Final_final_test\mywork\@fto@d\verilog.psm, 5440 , 2017-12-06
Final_final_test\mywork\@fto@d\_primary.dat, 401 , 2017-12-06
Final_final_test\mywork\@fto@d\_primary.dbs, 623 , 2017-12-06
Final_final_test\mywork\@fto@d\_primary.vhd, 508 , 2017-12-06
Final_final_test\mywork\@hazard@unit\verilog.prw, 712 , 2017-12-06
Final_final_test\mywork\@hazard@unit\verilog.psm, 11672 , 2017-12-06
Final_final_test\mywork\@hazard@unit\_primary.dat, 798 , 2017-12-06
Final_final_test\mywork\@hazard@unit\_primary.dbs, 1664 , 2017-12-06
Final_final_test\mywork\@hazard@unit\_primary.vhd, 850 , 2017-12-06
Final_final_test\mywork\@mto@w\verilog.prw, 415 , 2017-12-06
Final_final_test\mywork\@mto@w\verilog.psm, 8296 , 2017-12-06
Final_final_test\mywork\@mto@w\_primary.dat, 597 , 2017-12-06
Final_final_test\mywork\@mto@w\_primary.dbs, 954 , 2017-12-06
Final_final_test\mywork\@mto@w\_primary.vhd, 718 , 2017-12-06
Final_final_test\mywork\@p@c\verilog.prw, 540 , 2017-12-06
Final_final_test\mywork\@p@c\verilog.psm, 8568 , 2017-12-06
Final_final_test\mywork\@p@c\_primary.dat, 633 , 2017-12-06
Final_final_test\mywork\@p@c\_primary.dbs, 1178 , 2017-12-06
Final_final_test\mywork\@p@c\_primary.vhd, 610 , 2017-12-06
Final_final_test\mywork\@progra@mem\verilog.prw, 229 , 2017-12-06
Final_final_test\mywork\@progra@mem\verilog.psm, 3792 , 2017-12-06
Final_final_test\mywork\@progra@mem\_primary.dat, 298 , 2017-12-06
Final_final_test\mywork\@progra@mem\_primary.dbs, 434 , 2017-12-06
Final_final_test\mywork\@progra@mem\_primary.vhd, 220 , 2017-12-06
Final_final_test\mywork\@r@a@m\verilog.prw, 419 , 2017-12-06
Final_final_test\mywork\@r@a@m\verilog.psm, 8896 , 2017-12-06
Final_final_test\mywork\@r@a@m\_primary.dat, 594 , 2017-12-06
Final_final_test\mywork\@r@a@m\_primary.dbs, 903 , 2017-12-06
Final_final_test\mywork\@r@a@m\_primary.vhd, 543 , 2017-12-06
Final_final_test\mywork\@r@o@m\verilog.prw, 320 , 2017-12-06
Final_final_test\mywork\@r@o@m\verilog.psm, 5168 , 2017-12-06
Final_final_test\mywork\@r@o@m\_primary.dat, 385 , 2017-12-06
Final_final_test\mywork\@r@o@m\_primary.dbs, 606 , 2017-12-06
Final_final_test\mywork\@r@o@m\_primary.vhd, 314 , 2017-12-06
Final_final_test\mywork\@select@real@src@a@e\verilog.prw, 245 , 2017-12-06
Final_final_test\mywork\@select@real@src@a@e\verilog.psm, 4368 , 2017-12-06
Final_final_test\mywork\@select@real@src@a@e\_primary.dat, 345 , 2017-12-06
Final_final_test\mywork\@select@real@src@a@e\_primary.dbs, 545 , 2017-12-06
Final_final_test\mywork\@select@real@src@a@e\_primary.vhd, 420 , 2017-12-06
Final_final_test\mywork\@select@real@src@b@e\verilog.prw, 253 , 2017-12-06
Final_final_test\mywork\@select@real@src@b@e\verilog.psm, 4376 , 2017-12-06
Final_final_test\mywork\@select@real@src@b@e\_primary.dat, 349 , 2017-12-06
Final_final_test\mywork\@select@real@src@b@e\_primary.dbs, 549 , 2017-12-06
Final_final_test\mywork\@select@real@src@b@e\_primary.vhd, 420 , 2017-12-06
Final_final_test\mywork\@select@src@b\verilog.prw, 220 , 2017-12-06
Final_final_test\mywork\@select@src@b\verilog.psm, 3336 , 2017-12-06
Final_final_test\mywork\@select@src@b\_primary.dat, 240 , 2017-12-06
Final_final_test\mywork\@select@src@b\_primary.dbs, 441 , 2017-12-06
Final_final_test\mywork\@select@src@b\_primary.vhd, 328 , 2017-12-06
Final_final_test\mywork\@select@w@d3\verilog.prw, 220 , 2017-12-06
Final_final_test\mywork\@select@w@d3\verilog.psm, 3336 , 2017-12-06
Final_final_test\mywork\@select@w@d3\_primary.dat, 238 , 2017-12-06
Final_final_test\mywork\@select@w@d3\_primary.dbs, 438 , 2017-12-06
Final_final_test\mywork\@select@w@d3\_primary.vhd, 326 , 2017-12-06
Final_final_test\mywork\@select@write@addr3\verilog.prw, 197 , 2017-12-06
Final_final_test\mywork\@select@write@addr3\verilog.psm, 3368 , 2017-12-06
Final_final_test\mywork\@select@write@addr3\_primary.dat, 236 , 2017-12-06
Final_final_test\mywork\@select@write@addr3\_primary.dbs, 443 , 2017-12-06
Final_final_test\mywork\@select@write@addr3\_primary.vhd, 337 , 2017-12-06
Final_final_test\mywork\@sign@extend\verilog.prw, 219 , 2017-12-06