LogicSynthesis2_CMOSBasics
于 2014-07-07 发布
文件大小:1586KB
0 242
下载积分: 1
下载次数: 2
代码说明：
LogicSynthesis2_CMOSBasics Key Problem: Timing assumption during prelayout synthesis widely differs from the post layout reality. • This happens because the interconnect delay dominates the overall propagation delay in DSM (Deep Sub‐Micron) technologies. • As a result getting a timing closure becomes a challenge
下载说明：请别用迅雷下载，失败请重下，重下不扣分！
发表评论
