00786a_Driving-MOSFET-in-High-Current--Switch-Mod

（九宫问题）在一个３×３的九宫中有１－８这８个数及一个空格随机的摆放在其中的格子里，如图１－１所示。现在要求实现这个问题：将该九宫格调整为如图１－１右图所示的形式。调整的规则是：每次只能将与空格（上、下、或左、右）相邻的一个数字平移到空格中。试编程实现这一问题的求解。((Nine-palace issues) in a 3 × 3 of the Nine-palace are 1-8 this 8 random number and the placing of a space in which the cell house, as shown in Figure 1-1. Now required to achieve this issue: the squares adjustment for the right as shown in Figure 1-1 form. Adjustment of the rules: each can only be with the spaces (upper and lower, or left, right) adjacent to a digital flat space. Test Programming to solve this problem.)

协作通信中的基础仿真，含有pdf格式文章(cooperative communication Introduction and Simulation)

LTE ADVANCED ,LTE PHY Downlink with Spatial Multiplexing

SPMS deal 模块，SPMS deal 模——(SPMS deal 模块)

音频信号通过LM386放大，包括四元数的各种计算,D-S证据理论数据融合。( LM386 audio signal amplification, Including quaternion various calculations, D-S evidence theory data fusion.)

The future satellite communication systems are re- quired to support the higher transmission data rate for providing the multimedia services by employing the e铿僣ient modulation method such as multi-level QAM.

说明：  idunno wat am i doing

可以得到很精确的幅值、频率、相位估计，基于K均值的PSO聚类算法,光纤陀螺输出误差的allan方差分析。( You can get a very accurate amplitude, frequency, phase estimation, K-means clustering algorithm based on the PSO, allan FOG output error variance analysis.)

NS中文手册，不用多说，有兴趣的朋友都知道。找了很久终于找到了，很不错，感谢作者辛苦努力和无私奉献！(NS Chinese manual, Needless to say, friends who are interested to know. Looking for a long time finally found, it is good to thank the author of hard work and selfless dedication!)

本文研究了SMBus 规范，介绍了典型的基于片上系统（SoC）设计的知识产权核（IP）实现，采用自顶向下 (Top-down)的集成电路设计方法完成了设计，并架构了基于总线功能模型(BFM)的验证平台 完成功能仿真，顺利完成了逻辑综合和时序仿真。FPGA 验证和投片后测试均表明设计具有 良好的性能。(This paper studies the SMBus specification, based on the introduction of the typical system-on-chip (SoC) intellectual property core design (IP) implementation, using top-down (Top-down) of the integrated circuit design methods achieve a design and architecture based on the total Line functional model (BFM) achieve functional verification platform for simulation, successfully completed a logic synthesis and timing simulation. FPGA silicon validation and post-tests show that the design has good performance.)