FOURTH-ORDER-MUSIC

交织器的Matlab仿真，经过运行没有错误(Interleaver the Matlab simulation, after running no errors)

基于极限学习机的预测模型，数据为混沌数据(extreme learning machine)

通过matalb实现语音信号的处理，完成预加重、加窗函数、端点检测及生成处理后语音样本(Achieved by processing the speech signal matalb, complete the pre-emphasis, windowing function, voice activity detection and generation after sample processing)

对ＬＥＡＣＨ协议在ＭＡＴＬＡＢ里面仿真，以及改进的ＬＥＡＣＨ协议在ＭＡＴＬＡＢ里面仿真，之后对比(Simulation of LEACH protocol in MATLAB)

说明：  关于高层建筑强风条件下风压系数计算，整体风荷载评估(High-rise building on the strong wind conditions, wind pressure coefficients, the overall assessment of wind loads)

非线性系统模糊逻辑控制（FLC）的matlab仿真程序(Nonlinear systems fuzzy logic control (FLC) matlab simulation program)

无刷直流电机Matlab/Simulink仿真(BLDC Simulink simulation)

电力电子相关的仿真应用，直流无刷电机的控制仿真巧夺天工用诮顺(Simulation of power electronics-related applications, brushless DC motor control simulation of nature' s intricate use blame-shun)

这个程序是仿真加和不加golay编码的bpsk系统的ber及理论的ber，并在一个框图中分别给出对应的ber曲线.(This process is simulation plus and without Golay coded BPSK system theory ber and ber, and were given a diagram of the corresponding curve ber.)

在这项工作中,我们提出一个基于混沌的集成　　抖动升压电路用于多个振荡器抽样真的　　随机数发生器的架构。多个环形振荡器　　真正的随机数生成器需要大量　　戒指的积累内在抖动的逆变器　　有用的水平。因此,他们占领大的硅区域和消费　　大量的权力。该电路提供　　另一种方法推动使用混乱的抖动　　动态生成的两个环形振荡器的非线性耦合　　需要更少的组件的数量。的简单性　　提出了电路提供高集成和内在潜力　　面积和功耗低等优点。混沌动力学　　研究了电路的使用数值和电路　　模拟。测量测试芯片实现的结果　　250纳米CMOS技术(In this work, we present a chaos based integrated jitter booster circuit for use in multiple oscillator sampling true random number generator architecture. Multiple ring oscillator based true random number generators need significant number of rings for accumulating the intrinsic jitter of inverters to a useful level. Thus, they occupy large silicon area and consume considerable amount of power. The proposed circuit offers an alternative approach for boosting jitter using the chaotic dynamics generated by non-linear coupling of two ring oscillators that require fewer number of components. The simplicity of the proposed circuit offers high integration potential with inherent low area and power consumption advantages. Chaotic dynamics of the circuit was studied using both numerical and circuit simulations. Measurement results of the test chip implemented at 250nm CMOS technology node confirmed chaotic behavior and jitter boosting capability. To the very best of our knowled)