05473880

master thesis for wireless ad hoc network

Automatic Target Detection and tracking in FLIR Image sequences using Morphological connected operator

Bit error probability curve for QPSK mimo 2*1

this file talk about network

说明：  移动通信基础，经典介绍了移动通信最新技术及前沿动态。经典再现(Mobile Communication Foundation)

gardner位同步算法，实现数字通信系统中位同步(gardner bit synchronization algorithm to achieve bit synchronization in a digital communication system)

ARINC-美国航空无线电通信公司（Aeronautical Radio Inc），美国军队的长期合作伙伴。ARINC664系列协议是ARINC公司负责制定的下一代航空数据网络标准。该规范分为8个部分，从不同层次对航空数据网络标准的各个方面进行了系统的定义，形成了以AFDX技术为核心的下一代航空数据网络的完整标准。(ARINC-Aeronautical Radio Inc, the U.S. military long-term partners. ARINC664 series protocol is ARINC company is responsible for the formulation of the next generation of airborne data network standard. This specification is divided into eight parts, from different levels of airborne data network standard all aspects of the definition of the system, formed the AFDX technology at the core of the next generation of airborne data network complete standard.)

说明：  S7200 通过modbus 通讯与多块表通讯 定时轮询(Reading multi block instrument timing polling)

One issue with underwater sensors is how to efficiently transfer large amounts of data collected by the node to an interrogating platform such as an underwater vehicle. It is often impractical to make a physical connection between the node and the vehicle which suggests an acoustic or optical wireless solution. For large amounts of data, the high bandwidth of underwater optical wireless is an advantage. A small, low-cost platform to demonstrate the potential of an optical wireless communications interface for underwater sensor nodes is demonstrated. To enhance the reliability and robustness of the optical wireless communication digital signal processing and error correction techniques are used. The system was tested in 3 and 7.7 meter tanks at 5 Mbps with the turbidity of the water controlled by the addition of Maalox.

本文研究了SMBus 规范，介绍了典型的基于片上系统（SoC）设计的知识产权核（IP）实现，采用自顶向下 (Top-down)的集成电路设计方法完成了设计，并架构了基于总线功能模型(BFM)的验证平台 完成功能仿真，顺利完成了逻辑综合和时序仿真。FPGA 验证和投片后测试均表明设计具有 良好的性能。(This paper studies the SMBus specification, based on the introduction of the typical system-on-chip (SoC) intellectual property core design (IP) implementation, using top-down (Top-down) of the integrated circuit design methods achieve a design and architecture based on the total Line functional model (BFM) achieve functional verification platform for simulation, successfully completed a logic synthesis and timing simulation. FPGA silicon validation and post-tests show that the design has good performance.)