DVHOPSS

说明：  一个基础通信系统的M文件实现，包括产生信源，信源编码，调制，信道传输，解调和误码率绘图(Generate a Random Binary Data Stream. Modulate.White Gaussian Noise. Create a Scatter Plot. Compute the System s BER. )

滑模变结构配套例程(刘金昆)清华大学出版社无商业用途(Sliding mode matching routines (刘金昆) non-commercial purposes, Tsinghua University Press)

Piezo Sensons Application Note

对输入信号峰均比以及信号邻道泄露ACPR的处理(peak digitalsignal handle)

Data clustering using graph cut method

After identifying the best MNT− 1 nodes with the simplified branch metric and the accumulated branch metric at stage NT − 1, we then calculate the LLR of each coded bit utilizing the standard squared Euclidian distance metric. The log-likelihood ratio (LLR) of a posteriori probability (APP) of each coded bit conditioned on the received signal y is normally calculated using the max-log approximation.

matlab快速入门资料（word版），十分适宜于matlab的初学者。(Quick Start matlab data (word version), very suitable for matlab beginners.)

该程序用于实现零相位滤波,求系统的群延迟，调用格式大大简化，通俗易懂。(This is for everyone who is major in the communication project.)

直流电机双闭环控制系统matlab仿真程序(Motor double-loop control system simulation program Matlab)

触发器，eda.在实际的数字系统中往往包含大量的存储单元，而且经常要求他们在同一时刻同步动作，为达到这个目的，在每个存储单元电路上引入一个时钟脉冲（CLK）作为控制信号，只有当CLK到来时电路才被“触发”而动作，并根据输入信号改变输出状态。把这种在时钟信号触发时才能动作的存储单元电路称为触发器(Triggers, eda. The actual digital systems often contain a large number of memory cells, and at the same time they often require synchronized action, to achieve this purpose, the introduction of a clock pulse (CLK) in each memory cell circuit as a control signal , the arrival of the circuit only when CLK was only trigger the operation and change the output state of the input signal. The memory cell circuit that can trigger actions when the clock signal is called a flip-flop)