thewaveandpowerdestinyof2fsk

this is IMM tech. in tracking targets

Cisco 路由模拟配置 配置了OSPF BGP 等协议(Cisco router network simulation configuration documentation Configuring BGP routing protocols such as OSPF static)

This program named bloss obtains the B-coefficients of the loss formula as the function of real power generation. PL = P*B*P +B0*P +B00.

给出了简单的点到点CDMA系统的物理层和链路层联合仿真的Matlab程序。程序不长，但麻雀虽小，五脏据全。有详细的中文注释，相信一看就懂。(is a simple point-to-point system CDMA physical layer and link layer joint Matlab simulation procedures. Procedures are not long, but Sparrow Although small, but it was full. A detailed notes in Chinese, I believe one can understand it.)

求解tsp的改进遗传算法matlab源码(Improved Genetic Algorithms Matlab FOSS)

Identification system(IGls)

AR模型的Yule-Walker方程.1927年，Yule提出用线性回归方程来模拟一个时间序列。Yule的工作实际上成了现代谱估计中最重要的方法——参数模型法谱估计的基础。Walker利用Yule的分析方法研究了衰减正弦时间序列，得出Yule-Walker方程，可以说，Yule和Walker都是开拓自回归模型的先锋。(The Higher-Order Yule-Walker method.)

各种图论算法的matlab程序实现，包括floyd、hamilton、kruskal等(Various graph algorithm matlab program implementation, including floyd, hamilton, kruskal etc.)

cantera2.02 国外经典化学反应计算开源程序Cantera，基于MATLAB(cantera2.02 foreign classic chemical reaction open source Cantera, based on MATLAB)

在这项工作中,我们提出一个基于混沌的集成　　抖动升压电路用于多个振荡器抽样真的　　随机数发生器的架构。多个环形振荡器　　真正的随机数生成器需要大量　　戒指的积累内在抖动的逆变器　　有用的水平。因此,他们占领大的硅区域和消费　　大量的权力。该电路提供　　另一种方法推动使用混乱的抖动　　动态生成的两个环形振荡器的非线性耦合　　需要更少的组件的数量。的简单性　　提出了电路提供高集成和内在潜力　　面积和功耗低等优点。混沌动力学　　研究了电路的使用数值和电路　　模拟。测量测试芯片实现的结果　　250纳米CMOS技术(In this work, we present a chaos based integrated jitter booster circuit for use in multiple oscillator sampling true random number generator architecture. Multiple ring oscillator based true random number generators need significant number of rings for accumulating the intrinsic jitter of inverters to a useful level. Thus, they occupy large silicon area and consume considerable amount of power. The proposed circuit offers an alternative approach for boosting jitter using the chaotic dynamics generated by non-linear coupling of two ring oscillators that require fewer number of components. The simplicity of the proposed circuit offers high integration potential with inherent low area and power consumption advantages. Chaotic dynamics of the circuit was studied using both numerical and circuit simulations. Measurement results of the test chip implemented at 250nm CMOS technology node confirmed chaotic behavior and jitter boosting capability. To the very best of our knowled)