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TDTL_zero_order

于 2012-04-28 发布 文件大小:27KB
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代码说明:

  在matlab与SystemGenerator的平台下实现零阶时延数字正切锁相环。此模块最终能达到与输入信号同频率。(In the matlab, and SystemGenerator the platform, zero-order delay tangent digital phase-locked loop. This module is ultimately to reach input signal with the same frequency.)

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